Younghyun Lim

696 citations

25 papers · 499 indexed · h-index 13

Co-authors: Jaehyouk Choi Yongsun Lee Seyeon Yoo Juyeop Kim Yongwoo Jo Taeho Seong Heein Yoon Hangi Park
Topics: Radio Frequency Integrated Circuit Design (17 papers)Advancements in PLL and VCO Technologies (16 papers)Analog and Mixed-Signal Circuit Design (13 papers)
Cited by: Electrical and Electronic Engineering Biomedical Engineering Hardware and Architecture
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Transactions on Circuits & Systems II Express Briefs
Partner nations: South Korea United States

In The Last Decade

Younghyun Lim

21 papers receiving 484 citations

Peers

Countries citing papers authored by Younghyun Lim

Since Specialization

Citations

This map shows the geographic impact of Younghyun Lim's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Younghyun Lim with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Younghyun Lim more than expected).

Fields of papers citing papers by Younghyun Lim

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Younghyun Lim. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Younghyun Lim. The network helps show where Younghyun Lim may publish in the future.

Co-authorship network of co-authors of Younghyun Lim

This figure shows the co-authorship network connecting the top 25 collaborators of Younghyun Lim. A scholar is included among the top collaborators of Younghyun Lim based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Younghyun Lim. Younghyun Lim is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time 2025 ·(unknown),Moon‐Ku Han,(unknown),Younghyun Lim,Jaehyouk Choi	0
2	An Area-Efficient CMOS Cross-Coupled LC -VCO Using Nested Intertwined Tail Inductors 2024 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown),(unknown),(unknown),Younghyun Lim,Heein Yoon	0
3	A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop 2021 ·IEEE Journal of Solid-State Circuits ·Younghyun Lim,Juyeop Kim,Yongwoo Jo,(unknown),Jaehyouk Choi	15
4	32.4 A 104fs_rms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique 2021 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Juyeop Kim,Yongwoo Jo,Younghyun Lim,Taeho Seong,Hangi Park,Seyeon Yoo,Yongsun Lee,(unknown),Jaehyouk Choi	24
5	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator 2020 ·IEEE Journal of Solid-State Circuits ·Seyeon Yoo,(unknown),Yongsun Lee,Taeho Seong,Younghyun Lim,Jaehyouk Choi	16
6	17.8 A 170MHz-Lock-In-Range and −253dB-FoM_jitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator 2020 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Younghyun Lim,Juyeop Kim,Yongwoo Jo,(unknown),Seyeon Yoo,Hangi Park,Heein Yoon,Jaehyouk Choi	11
7	A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer 2019 ·IEEE Solid-State Circuits Letters ·(unknown),(unknown),Younghyun Lim,Seyeon Yoo,Yongsun Lee,Taeho Seong,Jaehyouk Choi	12
8	A 0.5V-V_IN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer 2019 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·(unknown),(unknown),Younghyun Lim,Jaehyouk Choi	7
9	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators 2019 ·IEEE Journal of Solid-State Circuits ·Juyeop Kim,Younghyun Lim,Heein Yoon,Yongsun Lee,Hangi Park,(unknown),Taeho Seong,Jaehyouk Choi	36
10	An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 2018 ·IEEE Journal of Solid-State Circuits ·(unknown),Seyeon Yoo,Yongsun Lee,Yongwoo Jo,(unknown),Younghyun Lim,Jaehyouk Choi	12
11	An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate 2018 ·Asia and South Pacific Design Automation Conference ·Younghyun Lim,(unknown),(unknown),Jaehyouk Choi	0
12	A −31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers 2018 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Heein Yoon,Juyeop Kim,(unknown),Younghyun Lim,Yongsun Lee,(unknown),(unknown),Jaehyouk Choi	46
13	153 FS<inf>RMS</inf>-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier 2018 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·(unknown),Seyeon Yoo,Yongsun Lee,Yongwoo Jo,(unknown),Younghyun Lim,Jaehyouk Choi	5
14	An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate 2018 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Younghyun Lim,(unknown),(unknown),Jaehyouk Choi	0
15	A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector 2018 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Younghyun Lim,(unknown),Yongsun Lee,Seyeon Yoo,Jaehyouk Choi	2
16	An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique 2018 ·IEEE Journal of Solid-State Circuits ·Younghyun Lim,(unknown),(unknown),Yongwoo Jo,Jaehyouk Choi	65
17	An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current 2017 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Younghyun Lim,(unknown),Yongsun Lee,Seong-Sik Song,Hong-Teuk Kim,Ockgoo Lee,Jaehyouk Choi	25
18	An extemal-capacitor-less low-dropout regulator with less than −36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate 2017 ·Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·Younghyun Lim,(unknown),(unknown),Jaehyouk Choi	19
19	A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G–4G Multistandard Cellular Transceivers 2016 ·IEEE Journal of Solid-State Circuits ·Heein Yoon,Yongsun Lee,Younghyun Lim,(unknown),Hong-Teuk Kim,Yo-Chuol Ho,Jaehyouk Choi	25
20	A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector 2016 ·IEEE Journal of Solid-State Circuits ·(unknown),Seyeon Yoo,Younghyun Lim,Jaehyouk Choi	77

About Younghyun Lim

Younghyun Lim is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Infectious Diseases, having authored 25 papers that have together received 499 indexed citations. Recurring topics across this work include Radio Frequency Integrated Circuit Design (17 papers), Advancements in PLL and VCO Technologies (16 papers) and Analog and Mixed-Signal Circuit Design (13 papers). The work is most often cited by research in Electrical and Electronic Engineering (493 citations), Biomedical Engineering (207 citations) and Hardware and Architecture (15 citations). Younghyun Lim has collaborated with scholars based in South Korea and United States. Frequent co-authors include Jaehyouk Choi, Yongsun Lee, Seyeon Yoo, Juyeop Kim, Yongwoo Jo, Taeho Seong, Heein Yoon, Hangi Park, Yo-Chuol Ho and Hong-Teuk Kim. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Transactions on Circuits & Systems II Express Briefs.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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