Romesh Kumar Nandwana

568 citations

27 papers · 424 indexed · h-index 11

Co-authors: Ahmed Elkholy Pavan Kumar Hanumolu Saurabh Saxena Amr Elshazly Robert C. N. Pilawa-Podgurski Qadeer Khan K.R. Lakshmikumar Mrunmay Talegaonkar
Topics: Advancements in PLL and VCO Technologies (20 papers)Photonic and Optical Devices (13 papers)Radio Frequency Integrated Circuit Design (10 papers)
Cited by: Electrical and Electronic Engineering Biomedical Engineering Hardware and Architecture
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Circuits and Systems I Regular Papers IEEE Transactions on Circuits & Systems II Express Briefs
Partner nations: United States India United Kingdom

In The Last Decade

Romesh Kumar Nandwana

26 papers receiving 418 citations

Peers

Countries citing papers authored by Romesh Kumar Nandwana

Since Specialization

Citations

This map shows the geographic impact of Romesh Kumar Nandwana's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Romesh Kumar Nandwana with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Romesh Kumar Nandwana more than expected).

Fields of papers citing papers by Romesh Kumar Nandwana

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Romesh Kumar Nandwana. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Romesh Kumar Nandwana. The network helps show where Romesh Kumar Nandwana may publish in the future.

Co-authorship network of co-authors of Romesh Kumar Nandwana

This figure shows the co-authorship network connecting the top 25 collaborators of Romesh Kumar Nandwana. A scholar is included among the top collaborators of Romesh Kumar Nandwana based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Romesh Kumar Nandwana. Romesh Kumar Nandwana is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling 2021 ·IEEE Journal of Solid-State Circuits ·Mostafa G. Ahmed,(unknown),Romesh Kumar Nandwana,Ahmed Elkholy,K.R. Lakshmikumar,Pavan Kumar Hanumolu	12
2	An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor 2021 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown),Romesh Kumar Nandwana,K.R. Lakshmikumar	4
3	A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/$\lambda$ PAM-4 Optical Links 2019 ·IEEE Journal of Solid-State Circuits ·K.R. Lakshmikumar,(unknown),Manohar Nagaraju,(unknown),Romesh Kumar Nandwana,(unknown),V. Boccuzzi	46
4	A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler 2019 ·IEEE Journal of Solid-State Circuits ·Ahmed Elkholy,(unknown),Romesh Kumar Nandwana,(unknown),Pavan Kumar Hanumolu	35
5	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver 2017 ·IEEE Journal of Solid-State Circuits ·Saurabh Saxena,Guanghua Shu,Romesh Kumar Nandwana,Mrunmay Talegaonkar,Ahmed Elkholy,Tejasvi Anand,Woo‐Seok Choi,Pavan Kumar Hanumolu	12
6	A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3ps<inf>rms</inf> period jitter in 65nm CMOS 2017 ·Seoul National University Open Repository (Seoul National University) ·(unknown),(unknown),Guanghua Shu,Woo‐Seok Choi,Romesh Kumar Nandwana,Ahmed Elkholy,(unknown),Pavan Kumar Hanumolu	0
7	8.6 A 2.5-to-5.75GHz 5mW 0.3ps<inf>rms</inf>-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS 2017 ·(unknown),Ahmed Elkholy,Romesh Kumar Nandwana,(unknown),Pavan Kumar Hanumolu	33
8	A 0.7V time-based inductor for fully integrated low bandwidth filter applications 2017 ·(unknown),Mrunmay Talegaonkar,Guanghua Shu,(unknown),Romesh Kumar Nandwana,(unknown),Pavan Kumar Hanumolu	2
9	A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS 2017 ·IEEE Journal of Solid-State Circuits ·Mrunmay Talegaonkar,Tejasvi Anand,Ahmed Elkholy,Amr Elshazly,Romesh Kumar Nandwana,Saurabh Saxena,Brian Young,Woo‐Seok Choi,Pavan Kumar Hanumolu	8
10	A 0.0021 mm²1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS 2016 ·IEEE Journal of Solid-State Circuits ·(unknown),Romesh Kumar Nandwana,Guanghua Shu,Ahmed Elkholy,(unknown),Pavan Kumar Hanumolu	26
11	19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS 2016 ·(unknown),Romesh Kumar Nandwana,Guanghua Shu,Ahmed Elkholy,Seong‐Joong Kim,Pavan Kumar Hanumolu	12
12	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS 2016 ·Guanghua Shu,Woo‐Seok Choi,Saurabh Saxena,Seong‐Joong Kim,Mrunmay Talegaonkar,Romesh Kumar Nandwana,Ahmed Elkholy,(unknown),(unknown),Pavan Kumar Hanumolu	5
13	A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC 2016 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Romesh Kumar Nandwana,Saurabh Saxena,Amr Elshazly,Kartikeya Mayaram,Pavan Kumar Hanumolu	10
14	A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator 2015 ·IEEE Journal of Solid-State Circuits ·(unknown),Romesh Kumar Nandwana,Qadeer Khan,Robert C. N. Pilawa-Podgurski,Pavan Kumar Hanumolu	48
15	12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS 2015 ·(unknown),Romesh Kumar Nandwana,Qadeer Khan,Robert C. N. Pilawa-Podgurski,Pavan Kumar Hanumolu	8
16	A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9ps<inf>rms</inf> integrated-jitter 2015 ·Ahmed Elkholy,Saurabh Saxena,Romesh Kumar Nandwana,Amr Elshazly,Pavan Kumar Hanumolu	3
17	A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement 2014 ·Romesh Kumar Nandwana,Tejasvi Anand,Saurabh Saxena,Seong‐Joong Kim,Mrunmay Talegaonkar,Ahmed Elkholy,WooSeok Choi,Amr Elshazly,Pavan Kumar Hanumolu	3
18	A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis 2014 ·IEEE Journal of Solid-State Circuits ·Saurabh Saxena,Romesh Kumar Nandwana,Pavan Kumar Hanumolu	30
19	A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC 2013 ·Romesh Kumar Nandwana,Saurabh Saxena,Amr Elshazly,Kartikeya Mayaram,Pavan Kumar Hanumolu	1
20	A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter 2013 ·Saurabh Saxena,Romesh Kumar Nandwana,Pavan Kumar Hanumolu	1

About Romesh Kumar Nandwana

Romesh Kumar Nandwana is a scholar working on Electrical and Electronic Engineering, Instrumentation and Biomedical Engineering, having authored 27 papers that have together received 424 indexed citations. Recurring topics across this work include Advancements in PLL and VCO Technologies (20 papers), Photonic and Optical Devices (13 papers) and Radio Frequency Integrated Circuit Design (10 papers). The work is most often cited by research in Electrical and Electronic Engineering (420 citations), Biomedical Engineering (158 citations) and Hardware and Architecture (12 citations). Romesh Kumar Nandwana has collaborated with scholars based in United States, India and United Kingdom. Frequent co-authors include Ahmed Elkholy, Pavan Kumar Hanumolu, Saurabh Saxena, Pavan Kumar Hanumolu, Amr Elshazly, Robert C. N. Pilawa-Podgurski, Qadeer Khan, K.R. Lakshmikumar, Mrunmay Talegaonkar and Guanghua Shu. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Circuits & Systems II Express Briefs.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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