Mario Mercandelli

465 total citations
19 papers, 359 citations indexed

About

Mario Mercandelli is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Infectious Diseases. According to data from OpenAlex, Mario Mercandelli has authored 19 papers receiving a total of 359 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 6 papers in Biomedical Engineering and 0 papers in Infectious Diseases. Recurrent topics in Mario Mercandelli's work include Advancements in PLL and VCO Technologies (17 papers), Radio Frequency Integrated Circuit Design (13 papers) and Semiconductor Lasers and Optical Devices (7 papers). Mario Mercandelli is often cited by papers focused on Advancements in PLL and VCO Technologies (17 papers), Radio Frequency Integrated Circuit Design (13 papers) and Semiconductor Lasers and Optical Devices (7 papers). Mario Mercandelli collaborates with scholars based in Italy, Austria and Ireland. Mario Mercandelli's co-authors include Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, Alessio Santiccioli, Luca Bertulessi, Dmytro Cherniak, Michael Peter Kennedy, Luigi Grimaldi, Andrea Bonfanti and Fabio Padovan and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Microwave and Wireless Components Letters.

In The Last Decade

Mario Mercandelli

19 papers receiving 357 citations

Peers

Mario Mercandelli
Sang Won Son South Korea
Hangi Park South Korea
Romesh Kumar Nandwana United States
Taeho Seong South Korea
Jaewook Shin South Korea
Mario Mercandelli
Citations per year, relative to Mario Mercandelli Mario Mercandelli (= 1×) peers Alessio Santiccioli

Countries citing papers authored by Mario Mercandelli

Since Specialization
Citations

This map shows the geographic impact of Mario Mercandelli's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mario Mercandelli with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mario Mercandelli more than expected).

Fields of papers citing papers by Mario Mercandelli

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mario Mercandelli. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mario Mercandelli. The network helps show where Mario Mercandelli may publish in the future.

Co-authorship network of co-authors of Mario Mercandelli

This figure shows the co-authorship network connecting the top 25 collaborators of Mario Mercandelli. A scholar is included among the top collaborators of Mario Mercandelli based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Mario Mercandelli. Mario Mercandelli is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

19 of 19 papers shown
1.
Bertulessi, Luca, Dmytro Cherniak, Mario Mercandelli, et al.. (2022). Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Transactions on Circuits and Systems I Regular Papers. 69(5). 1858–1870. 6 indexed citations
2.
Bertulessi, Luca, Mario Mercandelli, Andrea L. Lacaita, et al.. (2022). A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Transactions on Circuits & Systems II Express Briefs. 69(9). 3645–3649. 10 indexed citations
3.
Mercandelli, Mario, Luca Bertulessi, Carlo Samori, & Salvatore Levantino. (2022). A Digital PLL With Multitap LMS-Based Bandwidth Control. IEEE Solid-State Circuits Letters. 5. 126–129. 4 indexed citations
4.
Bertulessi, Luca, et al.. (2022). A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 20–24. 4 indexed citations
5.
Mercandelli, Mario, Alessio Santiccioli, Luca Bertulessi, et al.. (2021). A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE Journal of Solid-State Circuits. 57(2). 505–517. 41 indexed citations
6.
Mercandelli, Mario, et al.. (2021). Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators. IEEE Microwave and Wireless Components Letters. 31(9). 1075–1078. 3 indexed citations
7.
Mercandelli, Mario, Alessio Santiccioli, Luca Bertulessi, et al.. (2021). A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE Journal of Solid-State Circuits. 57(6). 1723–1735. 21 indexed citations
8.
Mercandelli, Mario, et al.. (2021). A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Transactions on Circuits and Systems I Regular Papers. 68(7). 2775–2786. 31 indexed citations
9.
Mercandelli, Mario, et al.. (2021). A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 67–70. 11 indexed citations
10.
Mercandelli, Mario, Alessio Santiccioli, Luca Bertulessi, et al.. (2021). 32.3 A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 445–447. 18 indexed citations
11.
Santiccioli, Alessio, Mario Mercandelli, Luca Bertulessi, et al.. (2021). 32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 456–458. 13 indexed citations
12.
Mercandelli, Mario, Luca Bertulessi, Carlo Samori, & Salvatore Levantino. (2021). A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 1–3. 3 indexed citations
13.
Santiccioli, Alessio, Mario Mercandelli, Luca Bertulessi, et al.. (2020). A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE Journal of Solid-State Circuits. 55(12). 3349–3361. 65 indexed citations
14.
Mercandelli, Mario, Alessio Santiccioli, Luca Bertulessi, et al.. (2020). 17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 274–276. 39 indexed citations
15.
Cherniak, Dmytro, Mario Mercandelli, Luca Bertulessi, et al.. (2020). A 250-Mb/s Direct Phase Modulator With −42.4-dB EVM Based on a 14-GHz Digital PLL. IEEE Solid-State Circuits Letters. 3. 126–129. 3 indexed citations
16.
Santiccioli, Alessio, Mario Mercandelli, Luca Bertulessi, et al.. (2020). 17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 268–270. 20 indexed citations
17.
Santiccioli, Alessio, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, & Salvatore Levantino. (2019). A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE Journal of Solid-State Circuits. 54(11). 3149–3160. 36 indexed citations
18.
Santiccioli, Alessio, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, & Salvatore Levantino. (2019). A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. Virtual Community of Pathological Anatomy (University of Castilla La Mancha). 1–4. 11 indexed citations
19.
Mercandelli, Mario, Luigi Grimaldi, Luca Bertulessi, et al.. (2018). A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE Journal of Solid-State Circuits. 53(11). 3243–3255. 20 indexed citations

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