Stephan Eggersglüß

566 total citations
36 papers, 408 citations indexed

About

Stephan Eggersglüß is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics. According to data from OpenAlex, Stephan Eggersglüß has authored 36 papers receiving a total of 408 indexed citations (citations by other indexed papers that have themselves been cited), including 31 papers in Hardware and Architecture, 24 papers in Electrical and Electronic Engineering and 15 papers in Computational Theory and Mathematics. Recurrent topics in Stephan Eggersglüß's work include VLSI and Analog Circuit Testing (31 papers), Integrated Circuits and Semiconductor Failure Analysis (17 papers) and Formal Methods in Verification (14 papers). Stephan Eggersglüß is often cited by papers focused on VLSI and Analog Circuit Testing (31 papers), Integrated Circuits and Semiconductor Failure Analysis (17 papers) and Formal Methods in Verification (14 papers). Stephan Eggersglüß collaborates with scholars based in Germany, United States and Netherlands. Stephan Eggersglüß's co-authors include Rolf Drechsler, Robert Wille, Görschwin Fey, Friedrich Hapke, Juergen Schloeffel, Andreas Glowatz, Daniel Große, Xiaoqing Wen, Kohei Miyase and Krishnendu Chakrabarty and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Design and Test.

In The Last Decade

Stephan Eggersglüß

34 papers receiving 394 citations

Peers

Countries citing papers authored by Stephan Eggersglüß

Since Specialization

Citations

This map shows the geographic impact of Stephan Eggersglüß's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Stephan Eggersglüß with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Stephan Eggersglüß more than expected).

Fields of papers citing papers by Stephan Eggersglüß

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Stephan Eggersglüß. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Stephan Eggersglüß. The network helps show where Stephan Eggersglüß may publish in the future.

Co-authorship network of co-authors of Stephan Eggersglüß

This figure shows the co-authorship network connecting the top 25 collaborators of Stephan Eggersglüß. A scholar is included among the top collaborators of Stephan Eggersglüß based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Stephan Eggersglüß. Stephan Eggersglüß is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Cell-aware Transistor State Stress Model and its Application for Quality Measurement 2024 ·Stephan Eggersglüß, Andreas Glowatz	0
2	A New Static Compaction of Deterministic Test Sets 2023 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Stephan Eggersglüß, (unknown), Janusz Rajski, Jerzy Tyszer	4
3	The Future of Design for Test and Silicon Lifecycle Management 2023 ·IEEE Design and Test ·Janusz Rajski, Vivek Chickermane, (unknown), Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer	10
4	Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing 2018 ·(unknown), Stephan Eggersglüß, Rolf Drechsler, (unknown), (unknown)	3
5	On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets 2016 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Stephan Eggersglüß, (unknown), (unknown), Rolf Drechsler	18
6	SAT-based post-processing for regional capture power reduction in at-speed scan test generation 2016 ·Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen	7
7	Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets 2014 ·Journal of Electronic Testing ·Stephan Eggersglüß	3
8	Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization 2014 ·Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer	10
9	Improved SAT-based ATPG: more constraints, better compaction 2013 ·International Conference on Computer Aided Design ·Stephan Eggersglüß, Robert Wille, Rolf Drechsler	31
10	Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill 2013 ·Stephan Eggersglüß	5
11	Improved SAT-based ATPG: More constraints, better compaction 2013 ·Stephan Eggersglüß, Robert Wille, Rolf Drechsler	37
12	MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics 2010 ·Journal of Electronic Testing ·Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler	13
13	Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability 2010 ·Stephan Eggersglüß, Rolf Drechsler	6
14	Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation 2010 ·Stephan Eggersglüß, (unknown), Rolf Drechsler	2
15	Structural heuristics for SAT-based ATPG 2009 ·(unknown), Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler	1
16	SWORD: A SAT like Prover Using Word Level Information 2009 ·IFIP International Federation for Information Processing/IFIP ·Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler	1
17	On Acceleration of SAT-Based ATPG for Industrial Designs 2008 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, (unknown)	81
18	Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults 2007 ·Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel	8
19	Studies on Integrating SAT-based ATPG in an Industrial Environment 2007 ·(unknown), Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, (unknown)	2
20	Improving Test Pattern Compactness in SAT-based ATPG 2007 ·Stephan Eggersglüß, Rolf Drechsler	15

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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