Pavan Kumar Hanumolu

2.4k citations

101 papers · 1.8k indexed · h-index 27

Electrical and Electronic Engineering top 2%
Biomedical Engineering top 2%
Automotive Engineering top 10%
Computer Networks and Communications top 10%
Cellular and Molecular Neuroscience

Co-authors: Sachin Rao Amr Elshazly Un-Ku Moon Ahmed Elkholy Brian Young Robert C. N. Pilawa-Podgurski Mrunmay Talegaonkar Kartikeya Mayaram
Topics: Analog and Mixed-Signal Circuit Design (61 papers)Advancements in PLL and VCO Technologies (52 papers)Radio Frequency Integrated Circuit Design (33 papers)
Cited by: Electrical and Electronic Engineering Biomedical Engineering Hardware and Architecture
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Circuits and Systems I Regular Papers
Partner nations: United States South Korea Japan

In The Last Decade

Pavan Kumar Hanumolu

99 papers receiving 1.8k citations

Peers

Countries citing papers authored by Pavan Kumar Hanumolu

Since Specialization

Citations

This map shows the geographic impact of Pavan Kumar Hanumolu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Pavan Kumar Hanumolu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Pavan Kumar Hanumolu more than expected).

Fields of papers citing papers by Pavan Kumar Hanumolu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Pavan Kumar Hanumolu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Pavan Kumar Hanumolu. The network helps show where Pavan Kumar Hanumolu may publish in the future.

Co-authorship network of co-authors of Pavan Kumar Hanumolu

This figure shows the co-authorship network connecting the top 25 collaborators of Pavan Kumar Hanumolu. A scholar is included among the top collaborators of Pavan Kumar Hanumolu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Pavan Kumar Hanumolu. Pavan Kumar Hanumolu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation 2023 ·(unknown),(unknown),Mostafa G. Ahmed,Peter Deaville,Bonan Zhang,Naveen Verma,Pavan Kumar Hanumolu,Naresh R. Shanbhag	3
2	A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling 2021 ·IEEE Journal of Solid-State Circuits ·Mostafa G. Ahmed,(unknown),Romesh Kumar Nandwana,Ahmed Elkholy,K.R. Lakshmikumar,Pavan Kumar Hanumolu	12
3	Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS 2020 ·IEEE Journal of Solid-State Circuits ·Pourya Assem,Wen-Chuen Liu,Yutian Lei,Pavan Kumar Hanumolu,Robert C. N. Pilawa-Podgurski	38
4	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS 2020 ·IEEE Journal of Solid-State Circuits ·(unknown),Mostafa G. Ahmed,Woo‐Seok Choi,Ahmed Elkholy,Pavan Kumar Hanumolu	15
5	Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers 2018 ·Qadeer Khan,Seong‐Joong Kim,Pavan Kumar Hanumolu	2
6	A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3ps<inf>rms</inf> period jitter in 65nm CMOS 2017 ·Seoul National University Open Repository (Seoul National University) ·(unknown),(unknown),Guanghua Shu,Woo‐Seok Choi,Romesh Kumar Nandwana,Ahmed Elkholy,(unknown),Pavan Kumar Hanumolu	0
7	A 0.0021 mm²1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS 2016 ·IEEE Journal of Solid-State Circuits ·(unknown),Romesh Kumar Nandwana,Guanghua Shu,Ahmed Elkholy,(unknown),Pavan Kumar Hanumolu	26
8	A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator 2015 ·IEEE Journal of Solid-State Circuits ·(unknown),Romesh Kumar Nandwana,Qadeer Khan,Robert C. N. Pilawa-Podgurski,Pavan Kumar Hanumolu	48
9	12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS 2015 ·(unknown),Romesh Kumar Nandwana,Qadeer Khan,Robert C. N. Pilawa-Podgurski,Pavan Kumar Hanumolu	8
10	15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS 2014 ·Ahmed Elkholy,Amr Elshazly,Saurabh Saxena,Guanghua Shu,Pavan Kumar Hanumolu	21
11	A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW 2014 ·Qadeer Khan,(unknown),Mrunmay Talegaonkar,Amr Elshazly,Arun Rao,(unknown),(unknown),(unknown),Pavan Kumar Hanumolu	3
12	Calibration technique for SAR analog-to-digital converters 2012 ·(unknown),(unknown),Pavan Kumar Hanumolu,Gábor C. Temes	2
13	A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity 2012 ·Amr Elshazly,Rajesh Inti,Mrunmay Talegaonkar,Pavan Kumar Hanumolu	3
14	A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration 2011 ·IEEE Journal of Solid-State Circuits ·Amr Elshazly,Rajesh Inti,Wenjing Yin,Brian Young,Pavan Kumar Hanumolu	40
15	A continuous-time input pipeline ADC with inherent anti-alias filtering 2009 ·David Gubbins,(unknown),(unknown),Pavan Kumar Hanumolu,Un-Ku Moon	2
16	Sensitivity Analysis for Oscillators 2008 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),David C. Lee,Pavan Kumar Hanumolu,Un-Ku Moon,Kartikeya Mayaram	13
17	Periodic Steady-State Analysis Augmented with Design Equality Constraints 2008 ·2008 Design, Automation and Test in Europe ·(unknown),Pavan Kumar Hanumolu,Un-Ku Moon,Kartikeya Mayaram	1
18	A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing 2007 ·(unknown),(unknown),Seiji Takeuchi,Koichi Hamashita,K. Takasuka,Pavan Kumar Hanumolu,Un-Ku Moon	7
19	A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC 2006 ·(unknown),Gil‐Cho Ahn,Pavan Kumar Hanumolu,Sang‐Hyeon Lee,(unknown),(unknown),(unknown),Gábor C. Temes,Un-Ku Moon	5
20	An FMDLL Based Dual-Loop Frequency Synthesizer for 5GHz WLAN Applications 2005 ·Ting Wu,Pavan Kumar Hanumolu,Un-Ku Moon,Kartikeya Mayaram	3

About Pavan Kumar Hanumolu

Pavan Kumar Hanumolu is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Bioengineering, having authored 101 papers that have together received 1.8k indexed citations. Recurring topics across this work include Analog and Mixed-Signal Circuit Design (61 papers), Advancements in PLL and VCO Technologies (52 papers) and Radio Frequency Integrated Circuit Design (33 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.7k citations), Biomedical Engineering (989 citations) and Hardware and Architecture (42 citations). Pavan Kumar Hanumolu has collaborated with scholars based in United States, South Korea and Japan. Frequent co-authors include Sachin Rao, Amr Elshazly, Un-Ku Moon, Ahmed Elkholy, Brian Young, Robert C. N. Pilawa-Podgurski, Mrunmay Talegaonkar, Kartikeya Mayaram, Romesh Kumar Nandwana and Mostafa G. Ahmed. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Circuits and Systems I Regular Papers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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