Anirban Sengupta

1.9k total citations
159 papers, 1.2k citations indexed

About

Anirban Sengupta is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Signal Processing. According to data from OpenAlex, Anirban Sengupta has authored 159 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 137 papers in Hardware and Architecture, 82 papers in Electrical and Electronic Engineering and 37 papers in Signal Processing. Recurrent topics in Anirban Sengupta's work include Physical Unclonable Functions (PUFs) and Hardware Security (94 papers), Embedded Systems Design Techniques (35 papers) and Integrated Circuits and Semiconductor Failure Analysis (29 papers). Anirban Sengupta is often cited by papers focused on Physical Unclonable Functions (PUFs) and Hardware Security (94 papers), Embedded Systems Design Techniques (35 papers) and Integrated Circuits and Semiconductor Failure Analysis (29 papers). Anirban Sengupta collaborates with scholars based in India, Canada and United States. Anirban Sengupta's co-authors include Saraju P. Mohanty, Reza Sedaghat, Vipul Kumar Mishra, Zhipeng Zeng, Chip-Hong Chang, Wei Hu, Ryan Kastner, Swarup Bhunia, Hai Li and Peter Corcoran and has published in prestigious journals such as Scientific Reports, Expert Systems with Applications and IEEE Access.

In The Last Decade

Anirban Sengupta

140 papers receiving 1.2k citations

Peers

Countries citing papers authored by Anirban Sengupta

Since Specialization

Citations

This map shows the geographic impact of Anirban Sengupta's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anirban Sengupta with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anirban Sengupta more than expected).

Fields of papers citing papers by Anirban Sengupta

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Anirban Sengupta. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anirban Sengupta. The network helps show where Anirban Sengupta may publish in the future.

Co-authorship network of co-authors of Anirban Sengupta

This figure shows the co-authorship network connecting the top 25 collaborators of Anirban Sengupta. A scholar is included among the top collaborators of Anirban Sengupta based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Anirban Sengupta. Anirban Sengupta is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Secure implantable cardiac pacemaker for medical consumer electronics 2025 ·Anirban Sengupta, (unknown)	2
2	Exploring low overhead fingerprint biometric watermark for loop pipelined hardware IPs during behavioral synthesis 2025 ·Journal of Information Security and Applications ·Anirban Sengupta, (unknown)	0
3	Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature 2024 ·Microprocessors and Microsystems ·Anirban Sengupta, (unknown), Ayush Singh	0
4	A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches 2024 ·IEEE Design and Test ·Anirban Sengupta, (unknown)	3
5	Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector 2024 ·Scientific Reports ·Anirban Sengupta, (unknown)	2
6	Gen-Sign: HLS Based Watermarking Using IP Vendor's Feistel Cipher Encrypted Genomic Signature for Protecting CNN and Image Processing Filter Cores Against Piracy 2024 ·Anirban Sengupta, (unknown), Ayush Singh	0
7	Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation 2024 ·Anirban Sengupta, (unknown), (unknown), Nitish Kumar	1
8	Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy 2024 ·Scientific Reports ·Anirban Sengupta, (unknown), (unknown), (unknown)	1
9	Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework 2024 ·IEEE Access ·Anirban Sengupta, (unknown)	2
10	HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning 2023 ·The Journal of Engineering ·Anirban Sengupta, (unknown), (unknown)	1
11	Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO 2023 ·(unknown), Anirban Sengupta	1
12	PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis 2023 ·Expert Systems with Applications ·(unknown), Anirban Sengupta	6
13	Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs 2023 ·Computers & Electrical Engineering ·Anirban Sengupta, (unknown), (unknown)	0
14	Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics 2023 ·(unknown), Anirban Sengupta	0
15	Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters 2023 ·Anirban Sengupta, (unknown), (unknown), (unknown)	1
16	Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing 2022 ·(unknown), Anirban Sengupta	2
17	Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core 2022 ·(unknown), Anirban Sengupta	1
18	VLSI design and test : 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019 : revised selected papers 2019 ·Springer eBooks ·Anirban Sengupta	1
19	Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors 2016 ·Microelectronics Reliability ·(unknown), Anirban Sengupta	11
20	Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm 2014 ·Anirban Sengupta, (unknown)	9

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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