Mark Tehranipoor
- Hardware and Architecture top 0.1%
- Physical Unclonable Functions (PUFs) and Hardware Security 170
- VLSI and Analog Circuit Testing 35
- Signal Processing top 1%
- Advanced Malware Detection Techniques 38
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- Integrated Circuits and Semiconductor Failure Analysis 101
- Advanced Memory and Neural Computing 21
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- Neuroscience and Neural Engineering 33
- Artificial Intelligence top 1%
- Security and Verification in Computing 43
- Cryptographic Implementations and Security 40
- Co-authors
- Domenic ForteSwarup BhuniaYier JinNavid AsadizanjaniUjjwal GuinBicky ShakyaJim PlusquellicZimu Guo
- Journals
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems (17 papers)ACM Transactions on Design Automation of Electronic Systems (11 papers)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (9 papers)
- Partner nations
- United StatesChinaFrance
In The Last Decade
Mark Tehranipoor
216 papers receiving 3.9k citations
Hit Papers
Peers
Comparison fields: 5 of 101
- Hardware and Architecture 2.9k
- Signal Processing 635
- Electrical and Electronic Engineering 2.5k
- Cellular and Molecular Neuroscience 667
- Artificial Intelligence 998
Countries citing papers authored by Mark Tehranipoor
This map shows the geographic impact of Mark Tehranipoor's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mark Tehranipoor with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mark Tehranipoor more than expected).
Fields of papers citing papers by Mark Tehranipoor
This network shows the impact of papers produced by Mark Tehranipoor. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mark Tehranipoor. The network helps show where Mark Tehranipoor may publish in the future.
Co-authorship network
The 25 scholars most cited alongside Mark Tehranipoor, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2024 | 0 | |
| 2 | 2024 | 2 | |
| 3 | LLM for SoC Security: A Paradigm Shiftbreakdown → | 2024 | 45 |
| 4 | 2023 | 10 | |
| 5 | 2023 | 0 | |
| 6 | 2023 | 9 | |
| 7 | 2023 | 8 | |
| 8 | 2023 | 2 | |
| 9 | 2023 | 2 | |
| 10 | 2022 | 13 | |
| 11 | 2021 | 5 | |
| 12 | 2021 | 11 | |
| 13 | 2020 | 1 | |
| 14 | 2019 | 20 | |
| 15 | 2018 | 14 | |
| 16 | 2018 | 4 | |
| 17 | 2017 | 45 | |
| 18 | 2017 | 17 | |
| 19 | 2016 | 36 | |
| 20 | 2014 | 21 |
About Mark Tehranipoor
Mark Tehranipoor is a scholar working on Hardware and Architecture, Signal Processing and Artificial Intelligence, having authored 223 papers that have together received 4.0k indexed citations. Recurring topics across this work include Physical Unclonable Functions (PUFs) and Hardware Security (170 papers), Integrated Circuits and Semiconductor Failure Analysis (101 papers), Security and Verification in Computing (43 papers), Cryptographic Implementations and Security (40 papers), Advanced Malware Detection Techniques (38 papers), VLSI and Analog Circuit Testing (35 papers), Neuroscience and Neural Engineering (33 papers) and Advanced Memory and Neural Computing (21 papers). The work is most often cited by research in Hardware and Architecture (2.9k citations), Signal Processing (635 citations) and Electrical and Electronic Engineering (2.5k citations). Mark Tehranipoor has collaborated with scholars based in United States, China and France. Frequent co-authors include Domenic Forte, Swarup Bhunia, Yier Jin, Navid Asadizanjani, Ujjwal Guin, Bicky Shakya, Jim Plusquellic, Zimu Guo, Farimah Farahmandi and Nima Karimian. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Journal on Emerging Technologies in Computing Systems and IEEE Design and Test.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.