Alan Mishchenko
- Electrical and Electronic Engineering top 2%
- Hardware and Architecture top 0.2%
- Computational Theory and Mathematics top 0.2%
- Artificial Intelligence top 1%
- Software top 1%
- Co-authors
- Robert K. BraytonSatrajit ChatterjeeMarek PerkowskiNiklas EénGiovanni De MicheliMathias SoekenSungmin ChoJie-Hong R. Jiang
- Topics
- Formal Methods in Verification (100 papers)VLSI and Analog Circuit Testing (91 papers)Low-power high-performance VLSI design (51 papers)
- Partner nations
- United StatesSwitzerlandTaiwan
In The Last Decade
Alan Mishchenko
160 papers receiving 2.9k citations
Hit Papers
Peers
Comparison fields: 5 of 54
- Electrical and Electronic Engineering 1.8k
- Hardware and Architecture 1.6k
- Computational Theory and Mathematics 1.6k
- Artificial Intelligence 872
- Software 379
Countries citing papers authored by Alan Mishchenko
This map shows the geographic impact of Alan Mishchenko's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Alan Mishchenko with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Alan Mishchenko more than expected).
Fields of papers citing papers by Alan Mishchenko
This network shows the impact of papers produced by Alan Mishchenko. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Alan Mishchenko. The network helps show where Alan Mishchenko may publish in the future.
Co-authorship network of co-authors of Alan Mishchenko
This figure shows the co-authorship network connecting the top 25 collaborators of Alan Mishchenko. A scholar is included among the top collaborators of Alan Mishchenko based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Alan Mishchenko. Alan Mishchenko is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | 2 | |
| 3 | 10 | |
| 4 | 6 | |
| 5 | 38 | |
| 6 | Clauses Versus Gates in CEGAR-Based 2QBF Solving. | 2 |
| 7 | 12 | |
| 8 | 3 | |
| 9 | 16 | |
| 10 | 14 | |
| 11 | 21 | |
| 12 | 11 | |
| 13 | 25 | |
| 14 | 28 | |
| 15 | 81 | |
| 16 | 34 | |
| 17 | 6 | |
| 18 | 92 | |
| 19 | 3 | |
| 20 | Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions | 1 |
About Alan Mishchenko
Alan Mishchenko is a scholar working on Hardware and Architecture, Computational Theory and Mathematics and Software, having authored 173 papers that have together received 3.1k indexed citations. Recurring topics across this work include Formal Methods in Verification (100 papers), VLSI and Analog Circuit Testing (91 papers) and Low-power high-performance VLSI design (51 papers). The work is most often cited by research in Hardware and Architecture (1.6k citations), Computational Theory and Mathematics (1.6k citations) and Software (379 citations). Alan Mishchenko has collaborated with scholars based in United States, Switzerland and Taiwan. Frequent co-authors include Robert K. Brayton, Satrajit Chatterjee, Marek Perkowski, Niklas Eén, Giovanni De Micheli, Mathias Soeken, Sungmin Cho, Jie-Hong R. Jiang, Bernd Steinbach and Lingli Wang. Their work appears in journals such as Proceedings of the IEEE, IEEE Access and IEEE Transactions on Computers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.