A.E. Dunlop

1.9k citations

17 papers · 1.0k indexed · h-index 12

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 5%
- VLSI and FPGA Design Techniques
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Optical Network Technologies

Papers in

Hardware and Architecture 9
- Embedded Systems Design Techniques 5
- VLSI and Analog Circuit Testing 3
- Parallel Computing and Optimization Techniques 2
Electrical and Electronic Engineering 15
- VLSI and FPGA Design Techniques 9
- Low-power high-performance VLSI design 8
- Photonic and Optical Devices 3
- Advancements in PLL and VCO Technologies 3

Co-authors: Brian W. Kernighan M. Banu J.P. Fishburn Vishwani D. Agrawal M. Wiesel P. Kozak Alberto Sangiovanni‐Vincentelli D.N. Deutsch
Journals: Computer (1 paper)IEEE Journal of Solid-State Circuits (1 paper)Journal of Lightwave Technology (1 paper)Electronics Letters (1 paper)Computer-Aided Design (1 paper)
Partner nations: United States

In The Last Decade

A.E. Dunlop

15 papers receiving 926 citations

Peers

Countries citing papers authored by A.E. Dunlop

Since Specialization

Citations

This map shows the geographic impact of A.E. Dunlop's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A.E. Dunlop with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A.E. Dunlop more than expected).

Fields of papers citing papers by A.E. Dunlop

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A.E. Dunlop. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A.E. Dunlop. The network helps show where A.E. Dunlop may publish in the future.

Co-authors

The 24 scholars most cited alongside A.E. Dunlop, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with A.E. Dunlop Line = papers co-authored together A.E. Dunlop links everyone, so they are left out of the graph.

All Works

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17 of 17 papers shown

#	Work
1	A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip A.E. Dunlop, T. Gabara, W.C. Fischer	2003	0
2	Experiments using automatic physical design techniques for optimizing circuit performance A.E. Dunlop, J.P. Fishburn, Dwight D. Hill, С. В. Арепьева	2003	0
3	150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection A.E. Dunlop, W.C. Fischer, M. Banu, T. Gabara	2002	15
4	Experiments using automatic physical design techniques for optimizing circuit performance A.E. Dunlop, J.P. Fishburn, Dwight D. Hill, С. В. Арепьева	2002	10
5	A set of switch-level synthesis tools Dwight D. Hill, С. В. Арепьева, A.E. Dunlop, J.P. Fishburn	2002	2
6	Tools and methodology for RF IC design A.E. Dunlop, Alper Demir, P. Feldmann, Sharad Kapur, David E. Long, Robert Melville, Jaijeet Roychowdhury	1998	16
7	Codesign from cospecification Computer ·Niharika Kamineni, A.E. Dunlop, Marilyn Wolf	1994	44
8	High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operation Journal of Lightwave Technology ·Yusuke Ota, R.G. Swartz, V.D. Archer, S.K. Korotky, M. Banu, A.E. Dunlop	1994	67
9	A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission M. Banu, A.E. Dunlop	1993	47
10	Clock recovery circuits with instantaneous locking Electronics Letters ·M. Banu, A.E. Dunlop	1992	30
11	Optimization-based transistor sizing IEEE Journal of Solid-State Circuits ·Bayyinah Bahar, Alberto Sangiovanni‐Vincentelli, J.P. Fishburn, A.E. Dunlop	1988	141
12	Cell-Based Layout Benchmarks Design Automation Conference ·A.E. Dunlop, Bryan Preas, Kevin Roberts	1987	5
13	A Procedure for Placement of Standard-Cell VLSI Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·A.E. Dunlop, Brian W. Kernighan	1985	360
14	Chip Layout Optimization Using Critical Path Weighting Design Automation Conference ·A.E. Dunlop, Vishwani D. Agrawal, D.N. Deutsch, 安敏芝, P. Kozak, M. Wiesel	1984	122
15	Chip Layout Optimization Using Critical Path Weighting A.E. Dunlop, Vishwani D. Agrawal, D.N. Deutsch, 安敏芝, P. Kozak, M. Wiesel	1984	86
16	SLIM-the translation of symbolic layouts into mask data A.E. Dunlop	1980	40
17	SLIP: symbolic layout of integrated circuits with compaction Computer-Aided Design ·A.E. Dunlop	1978	41

About A.E. Dunlop

A.E. Dunlop is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Biomedical Engineering, Computational Theory and Mathematics and Artificial Intelligence, having authored 17 papers that have together received 1.0k indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (9 papers), Low-power high-performance VLSI design (8 papers), Embedded Systems Design Techniques (5 papers), Photonic and Optical Devices (3 papers), VLSI and Analog Circuit Testing (3 papers), Analog and Mixed-Signal Circuit Design (3 papers), Advancements in PLL and VCO Technologies (3 papers) and Parallel Computing and Optimization Techniques (2 papers). The work is most often cited by research in Hardware and Architecture (600 citations), Electrical and Electronic Engineering (928 citations), Computer Graphics and Computer-Aided Design (28 citations), Computer Networks and Communications (157 citations) and Industrial and Manufacturing Engineering (51 citations). A.E. Dunlop has collaborated with scholars based in United States. Frequent co-authors include Brian W. Kernighan, M. Banu, J.P. Fishburn, Vishwani D. Agrawal, M. Wiesel, P. Kozak, Alberto Sangiovanni‐Vincentelli, D.N. Deutsch, Marilyn Wolf and Yusuke Ota. Their work appears in journals such as Computer, IEEE Journal of Solid-State Circuits, Journal of Lightwave Technology, Electronics Letters and Computer-Aided Design.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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