J. Keaty

1.2k citations

7 papers · 535 indexed · 1 hit paper · h-index 6

Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques 3
- Embedded Systems Design Techniques 2
- VLSI and Analog Circuit Testing 2
Computer Networks and Communications top 5%
- Interconnection Networks and Systems 3
Electrical and Electronic Engineering
- Low-power high-performance VLSI design 3
- Electromagnetic Compatibility and Noise Suppression 2
- Advancements in PLL and VCO Technologies 1
- VLSI and FPGA Design Techniques 1
Computer Graphics and Computer-Aided Design
Computer Vision and Pattern Recognition

Co-authors: C. Johns Atsushi Kameyama J. Warnock D. Wendel S. Weitzel H. Peter Hofstee Yoshio Masubuchi M. Riley
Cited by: Hardware and Architecture Computer Networks and Communications Electrical and Electronic Engineering
Journals: IEEE Journal of Solid-State Circuits (1 paper)IBM Journal of Research and Development (1 paper)
Partner nations: United States Japan

In The Last Decade

J. Keaty

7 papers receiving 491 citations

Hit Papers

align trajectories log scale

Peers

Countries citing papers authored by J. Keaty

Since Specialization

Citations

This map shows the geographic impact of J. Keaty's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Keaty with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Keaty more than expected).

Fields of papers citing papers by J. Keaty

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Keaty. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Keaty. The network helps show where J. Keaty may publish in the future.

Co-authorship network

The 25 scholars most cited alongside J. Keaty, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Keaty Line = papers co-authored together J. Keaty links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

7 of 7 papers shown

#	Work
1	A Resonant Global Clock Distribution for the Cell Broadband Engine Processor IEEE Journal of Solid-State Circuits ·S.C. Chan,P.J. Restle,T. Bucelot,J. S. Liberty,Stephen Weitzel,J. Keaty,B. Flachs,R. Volant,Peter Kapusta,Jeffrey S. Zimmerman	2009	32
2	A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor Steven H. Chan,P.J. Restle,T. Bucelot,Stephen Weitzel,J. Keaty,J. S. Liberty,B. Flachs,R. Volant,Peter Kapusta,J. Zimmerman	2008	18
3	Implementation of the 65nm Cell Broadband Engine M. Riley,B. Flachs,S.H. Dhong,G. Gervais,S. Weitzel,Mingjun Wang,D. Boerstler,M. Bolliger,J. Keaty,J. Pille,Robert F. Berry,Osamu Takahashi,Y. Nishino,Taku Uchino	2007	2
4	The design methodology and implementation of a first-generation CELL processor: a multi-core SoC D. Pham,E. Behnen,M. Bolliger,H. Peter Hofstee,C. Johns,J. Kahle,Atsushi Kameyama,J. Keaty,Bob Le,Yoshio Masubuchi,S. Posluszny,M. Riley,M. Suzuoki,M. Wang,J. Warnock,S. Weitzel,D. Wendel,Kazuaki Yazawa	2006	12
5	The design and implementation of a first-generation CELL processor - a multi-core SoC D. Pham,S. Asano,M. Bolliger,Michael Day,H. Peter Hofstee,C. Johns,J. Kahle,Atsushi Kameyama,J. Keaty,Yoshio Masubuchi,M. Riley,D. Shippy,D. Stasiak,M. Suzuoki,M. Wang,J. Warnock,S. Weitzel,D. Wendel,T. Yamazaki,Kazuaki Yazawa	2005	15
6	The design and implementation of a first-generation CELL processorbreakdown → D. Pham,S. Asano,M. Bolliger,Michael Day,H. Peter Hofstee,C. Johns,J. Kahle,Atsushi Kameyama,J. Keaty,Yoshio Masubuchi,M. Riley,D. Shippy,D. Stasiak,M. Suzuoki,Mingjun Wang,J. Warnock,S. Weitzel,D. Wendel,T. Yamazaki,Kazuaki Yazawa	2005	371
7	The circuit and physical design of the POWER4 microprocessor IBM Journal of Research and Development ·J.D. Warnock,J. Keaty,John G. Petrovick,J. Clabes,C. J. Kircher,B. Krauter,P.J. Restle,B. Zoric,C.J. Anderson	2002	85

About J. Keaty

J. Keaty is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 7 papers that have together received 535 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (3 papers), Interconnection Networks and Systems (3 papers), Parallel Computing and Optimization Techniques (3 papers), Electromagnetic Compatibility and Noise Suppression (2 papers), Embedded Systems Design Techniques (2 papers), VLSI and Analog Circuit Testing (2 papers), Advancements in PLL and VCO Technologies (1 paper) and VLSI and FPGA Design Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (333 citations), Computer Networks and Communications (245 citations) and Electrical and Electronic Engineering (273 citations). J. Keaty has collaborated with scholars based in United States and Japan. Frequent co-authors include C. Johns, Atsushi Kameyama, J. Warnock, D. Wendel, S. Weitzel, H. Peter Hofstee, Yoshio Masubuchi, M. Riley, M. Suzuoki and Kazuaki Yazawa. Their work appears in journals such as IEEE Journal of Solid-State Circuits and IBM Journal of Research and Development.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact