D. Pham
Impact in
- Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
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- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- Distributed and Parallel Computing Systems
Papers in
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- Parallel Computing and Optimization Techniques 3
- VLSI and Analog Circuit Testing 2
- Embedded Systems Design Techniques 1
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- Low-power high-performance VLSI design 2
- Semiconductor materials and devices 2
- VLSI and FPGA Design Techniques 1
- Advancements in PLL and VCO Technologies 1
- Co-authors
- J. Warnock (4 shared papers)D. Wendel (4 shared papers)S. Weitzel (3 shared papers)M. Suzuoki (3 shared papers)C. Johns (3 shared papers)M. Riley (3 shared papers)Yoshio Masubuchi (3 shared papers)Kazuaki Yazawa (3 shared papers)
- Partner nations
- United StatesJapanGermany
In The Last Decade
D. Pham
5 papers receiving 381 citations
Hit Papers
Peers
Comparison fields: 5 of 38
- Hardware and Architecture 296
- Computer Networks and Communications 230
- Computer Graphics and Computer-Aided Design 10
- Electrical and Electronic Engineering 159
- Computer Vision and Pattern Recognition 38
Countries citing papers authored by D. Pham
This map shows the geographic impact of D. Pham's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Pham with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Pham more than expected).
Fields of papers citing papers by D. Pham
This network shows the impact of papers produced by D. Pham. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Pham. The network helps show where D. Pham may publish in the future.
Co-authors
The 22 scholars most cited alongside D. Pham, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | The design and implementation of a first-generation CELL processor Hit paper breakdown → | 2005 | 371 |
| 2 | 2005 | 15 | |
| 3 | 2006 | 12 | |
| 4 | 2002 | 11 | |
| 5 | 2006 | 8 |
About D. Pham
D. Pham is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Infectious Diseases and Organic Chemistry, having authored 5 papers that have together received 417 indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (3 papers), Interconnection Networks and Systems (3 papers), Low-power high-performance VLSI design (2 papers), Semiconductor materials and devices (2 papers), VLSI and Analog Circuit Testing (2 papers), Embedded Systems Design Techniques (1 paper), VLSI and FPGA Design Techniques (1 paper) and Advancements in PLL and VCO Technologies (1 paper). The work is most often cited by research in Hardware and Architecture (296 citations), Computer Networks and Communications (230 citations), Computer Graphics and Computer-Aided Design (10 citations), Electrical and Electronic Engineering (159 citations) and Computer Vision and Pattern Recognition (38 citations). D. Pham has collaborated with scholars based in United States, Japan and Germany. Frequent co-authors include J. Warnock, D. Wendel, S. Weitzel, M. Suzuoki, C. Johns, M. Riley, Yoshio Masubuchi, Kazuaki Yazawa, J. Keaty and Atsushi Kameyama. Their work appears in journals such as IEEE Journal of Solid-State Circuits.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.