Jim Garside

3.1k total citations · 1 hit paper
87 papers, 2.0k citations indexed

About

Jim Garside is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Jim Garside has authored 87 papers receiving a total of 2.0k indexed citations (citations by other indexed papers that have themselves been cited), including 60 papers in Hardware and Architecture, 53 papers in Electrical and Electronic Engineering and 49 papers in Computer Networks and Communications. Recurrent topics in Jim Garside's work include Parallel Computing and Optimization Techniques (50 papers), Interconnection Networks and Systems (41 papers) and Low-power high-performance VLSI design (40 papers). Jim Garside is often cited by papers focused on Parallel Computing and Optimization Techniques (50 papers), Interconnection Networks and Systems (41 papers) and Low-power high-performance VLSI design (40 papers). Jim Garside collaborates with scholars based in United Kingdom, United States and China. Jim Garside's co-authors include Steve Furber, Steve Temple, Luis A. Plana, Eustace Painkras, A.D. Brown, David Lester, Aristides Efthymiou, N.C. Paver, P. Day and Cameron Patterson and has published in prestigious journals such as PLoS ONE, Proceedings of the IEEE and IEEE Access.

In The Last Decade

Jim Garside

84 papers receiving 1.9k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Overview of the SpiNNaker System Architecture

2012 440 citations Steve Furber, Luis A. Plana et al. profile →

Peers

Countries citing papers authored by Jim Garside

Since Specialization

Citations

This map shows the geographic impact of Jim Garside's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jim Garside with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jim Garside more than expected).

Fields of papers citing papers by Jim Garside

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jim Garside. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jim Garside. The network helps show where Jim Garside may publish in the future.

Co-authorship network of co-authors of Jim Garside

This figure shows the co-authorship network connecting the top 25 collaborators of Jim Garside. A scholar is included among the top collaborators of Jim Garside based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jim Garside. Jim Garside is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A novel approach to data integrity auditing in PCS: Minimising any Trust on Third Parties (DIA-MTTP) 2021 ·PLoS ONE ·(unknown), Ning Zhang, Jim Garside	1
2	An effective, secure and efficient tagging method for integrity protection of outsourced data in a public cloud storage 2020 ·PLoS ONE ·(unknown), (unknown), Jim Garside	6
3	Dynamic Power Management for Neuromorphic Many-Core Systems 2019 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Sebastian Höppner, Bernhard Vogginger, (unknown), (unknown), Stefan Scholze, Johannes Partzsch, (unknown), Stephan Hartmann, Stefan Schiefer, Georg Ellguth, (unknown), Luis A. Plana, Jim Garside, Steve Furber, Christian Mayr	15
4	Resource Elastic Virtualization for FPGAs Using OpenCL 2018 ·Research Explorer (The University of Manchester) ·(unknown), Khoa Dang Pham, Dirk Koch, Jim Garside	37
5	Parallel distribution of an inner hair cell and auditory nerve model for real-time application 2017 ·R. A. James, Jim Garside, (unknown), Luis A. Plana, Steve Temple, Simon Davidson, Steve Furber	3
6	Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip 2017 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, Zhiying Wang	4
7	Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation 2017 ·Research Explorer (The University of Manchester) ·(unknown), Jim Garside, Steve Furber, Luis A. Plana, Dirk Koch	2
8	De-elastisation: from asynchronous dataflows to synchronous circuits 2015 ·Design, Automation, and Test in Europe ·(unknown), Jim Garside, (unknown)	3
9	An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults 2014 ·Research Explorer (The University of Manchester) ·Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, Zhiying Wang	3
10	eTeak: A Data-driven Synchronous Elastic Synthesiser 2013 ·Research Explorer (The University of Manchester) ·Jim Garside, (unknown), (unknown)	5
11	SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation 2012 ·Research Explorer (The University of Manchester) ·Eustace Painkras, Luis A. Plana, Jim Garside, Steve Temple, Simon Davidson, (unknown), David Clark, Cameron Patterson, Steve Furber	50
12	Area efficient asynchronous SDM routers using 2-stage Clos switches 2012 ·Wei Song, (unknown), Jim Garside, W.J. Bainbridge	1
13	Architecture for Runtime Hardware Compilation 2011 ·Research Explorer (The University of Manchester) ·(unknown), Jim Garside	1
14	Reconfigurable latch controllers for low power asynchronous circuits 2003 ·Research Explorer (The University of Manchester) ·Mary Lewis, Jim Garside, (unknown)	11
15	AMULET3 revealed 2003 ·Research Explorer (The University of Manchester) ·Jim Garside, Steve Furber, (unknown)	22
16	T8: Logic Design of Asynchronous Circuits 2002 ·Asia and South Pacific Design Automation Conference ·Jordi Cortadella, Alex Yakovlev, Jim Garside	0
17	AMULET3i cache architecture 2002 ·Research Explorer (The University of Manchester) ·(unknown), Jim Garside	3
18	A result forwarding mechanism for asynchronous pipelined systems 2002 ·(unknown), Jim Garside	12
19	Power management in the Amulet microprocessors 2001 ·IEEE Design & Test of Computers ·Steve Furber, Aristides Efthymiou, Jim Garside, D.W. Lloyd, (unknown), Steve Temple	7
20	A micropipelined ARM 1993 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Steve Furber, P. Day, Jim Garside, N.C. Paver, J.V. Woods	59

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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