Tiberiu Chelcea

913 total citations
30 papers, 649 citations indexed

About

Tiberiu Chelcea is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Tiberiu Chelcea has authored 30 papers receiving a total of 649 indexed citations (citations by other indexed papers that have themselves been cited), including 28 papers in Hardware and Architecture, 18 papers in Computer Networks and Communications and 13 papers in Electrical and Electronic Engineering. Recurrent topics in Tiberiu Chelcea's work include Interconnection Networks and Systems (18 papers), Parallel Computing and Optimization Techniques (18 papers) and Embedded Systems Design Techniques (17 papers). Tiberiu Chelcea is often cited by papers focused on Interconnection Networks and Systems (18 papers), Parallel Computing and Optimization Techniques (18 papers) and Embedded Systems Design Techniques (17 papers). Tiberiu Chelcea collaborates with scholars based in United States, United Kingdom and Denmark. Tiberiu Chelcea's co-authors include Steven M. Nowick, Seth Copen Goldstein, Girish Venkataramani, Mihai Budiu, Timothy J. Callahan, D. Edwards and T. Bjerregaard and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM SIGPLAN Notices and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Tiberiu Chelcea

28 papers receiving 611 citations

Peers

Tiberiu Chelcea

CNC

EEE

CTM

Varghese George United States

M.K. Gowan United States

Jui-Ming Chang United States

Larry Biro United States

M.D. Noakes United States

P.E. Gronowski United States

R. Zafalon Italy

Girish Venkataramani United States

Nagu Dhanwada United States

Kwok-Shing Leung United States

Varghese George United States

Tiberiu Chelcea

513 ×0.9

411 ×0.9

CNC

550 ×1.7

EEE

19 ×0.5

CTM

12 ×0.7

Citations per year, relative to Tiberiu Chelcea Tiberiu Chelcea (= 1×) peers Varghese George

Countries citing papers authored by Tiberiu Chelcea

Since Specialization

Citations

This map shows the geographic impact of Tiberiu Chelcea's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tiberiu Chelcea with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tiberiu Chelcea more than expected).

Fields of papers citing papers by Tiberiu Chelcea

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tiberiu Chelcea. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tiberiu Chelcea. The network helps show where Tiberiu Chelcea may publish in the future.

Co-authorship network of co-authors of Tiberiu Chelcea

This figure shows the co-authorship network connecting the top 25 collaborators of Tiberiu Chelcea. A scholar is included among the top collaborators of Tiberiu Chelcea based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tiberiu Chelcea. Tiberiu Chelcea is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Venkataramani, Girish, Tiberiu Chelcea, & Seth Copen Goldstein. (2018). HLS Support for Unconstrained Memory Accesses. Research Showcase @ Carnegie Mellon University (Carnegie Mellon University).

Venkataramani, Girish, Tiberiu Chelcea, Mihai Budiu, & Seth Copen Goldstein. (2018). Modeling the Global Critical Path in Concurrent Systems. Research Showcase @ Carnegie Mellon University (Carnegie Mellon University). 16(3).

Venkataramani, Girish, Mihai Budiu, Tiberiu Chelcea, & Seth Copen Goldstein. (2018). C to Asynchronous Dataflow Circuits: An End-to-End Toolflow. Figshare. 6 indexed citations

Venkataramani, Girish, Mihai Budiu, Tiberiu Chelcea, & Seth Copen Goldstein. (2007). Critical Path: A Tool for System-Level Timing Analysis. Design Automation Conference. 2 indexed citations

Chelcea, Tiberiu, Girish Venkataramani, & Seth Copen Goldstein. (2007). Self-resetting latches for asynchronous micro-pipelines. Proceedings - ACM IEEE Design Automation Conference. 986–986. 8 indexed citations

Chelcea, Tiberiu, Girish Venkataramani, & Seth Copen Goldstein. (2007). Self-Resetting Latches for Asynchronous Micro-Pipelines. Proceedings - ACM IEEE Design Automation Conference. 986–989. 1 indexed citations

Venkataramani, Girish, Mihai Budiu, Tiberiu Chelcea, & Seth Copen Goldstein. (2007). Global Critical Path: A Tool for System-Level Timing Analysis. Proceedings - ACM IEEE Design Automation Conference. 783–786. 2 indexed citations

Chelcea, Tiberiu, Girish Venkataramani, & Seth Copen Goldstein. (2007). Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. 117–128. 8 indexed citations

Venkataramani, Girish, Mihai Budiu, Tiberiu Chelcea, & Seth Copen Goldstein. (2007). Global critical path. Proceedings - ACM IEEE Design Automation Conference. 783–783. 10 indexed citations

10.

Callahan, Timothy J., et al.. (2006). Tartan. 163–174. 68 indexed citations

11.

Venkataramani, Girish, Tiberiu Chelcea, Seth Copen Goldstein, & T. Bjerregaard. (2005). SOMA. 231–236. 7 indexed citations

12.

Budiu, Mihai, Girish Venkataramani, Tiberiu Chelcea, & Seth Copen Goldstein. (2004). Spatial computation. ACM SIGPLAN Notices. 39(11). 14–26. 4 indexed citations

13.

Budiu, Mihai, Girish Venkataramani, Tiberiu Chelcea, & Seth Copen Goldstein. (2004). Spatial computation. ACM SIGARCH Computer Architecture News. 32(5). 14–26. 2 indexed citations

14.

Chelcea, Tiberiu & Steven M. Nowick. (2004). Robust interfaces for mixed-timing systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12(8). 857–873. 103 indexed citations

15.

Chelcea, Tiberiu, et al.. (2002). A Burst-Mode Oriented Back-End for the Balsa Synthesis System. Design, Automation, and Test in Europe. 330–337. 16 indexed citations

16.

Chelcea, Tiberiu & Steven M. Nowick. (2002). A low-latency FIFO for mixed-clock systems. 119–126. 70 indexed citations

17.

Chelcea, Tiberiu & Steven M. Nowick. (2002). Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. 50 indexed citations

18.

Chelcea, Tiberiu & Steven M. Nowick. (2002). Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. Proceedings - ACM IEEE Design Automation Conference. 405–405. 30 indexed citations

19.

Chelcea, Tiberiu & Steven M. Nowick. (2002). Low-latency asynchronous FIFO's using token rings. 210–220. 22 indexed citations

20.

Chelcea, Tiberiu & Steven M. Nowick. (2001). Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. 21–26. 92 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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