Yung‐Chih Chen

1.7k citations

117 papers · 1.2k indexed · h-index 16

Electrical and Electronic Engineering top 5%
Computer Networks and Communications top 2%
Computer Vision and Pattern Recognition top 10%
Hardware and Architecture top 5%
Artificial Intelligence top 10%

Co-authors: Don Towsley Chun-Yao Wang Erich Nahum Yeon-sup Lim Chih‐Lung Lin Richard Gibbens Ramin Khalili Chia-Chun Lin
Topics: Low-power high-performance VLSI design (28 papers)Advanced Memory and Neural Computing (21 papers)VLSI and Analog Circuit Testing (20 papers)
Cited by: Computer Networks and Communications Hardware and Architecture Electrical and Electronic Engineering
Journals: IEEE Journal on Selected Areas in Communications RSC Advances IEEE Transactions on Circuits and Systems for Video Technology
Partner nations: Taiwan United States Germany

In The Last Decade

Yung‐Chih Chen

102 papers receiving 1.2k citations

Peers

Countries citing papers authored by Yung‐Chih Chen

Since Specialization

Citations

This map shows the geographic impact of Yung‐Chih Chen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yung‐Chih Chen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yung‐Chih Chen more than expected).

Fields of papers citing papers by Yung‐Chih Chen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yung‐Chih Chen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yung‐Chih Chen. The network helps show where Yung‐Chih Chen may publish in the future.

Co-authorship network of co-authors of Yung‐Chih Chen

This figure shows the co-authorship network connecting the top 25 collaborators of Yung‐Chih Chen. A scholar is included among the top collaborators of Yung‐Chih Chen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yung‐Chih Chen. Yung‐Chih Chen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage 2025 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown),Yung‐Chih Chen,(unknown)	0
2	A Hybrid Approach to Reverse Engineering on Combinational Circuits 2024 ·(unknown),Yiting Li,(unknown),(unknown),You-Cheng Lin,(unknown),(unknown),Yung‐Chih Chen,Ting-Chi Wang,Shih-Chieh Chang,TingTing Hwang,Chun-Yao Wang	0
3	9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function 2024 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),(unknown),Yiting Li,Yung‐Chih Chen,(unknown),Chun-Yao Wang	1
4	IR drop Prediction Based on Machine Learning and Pattern Reduction 2024 ·(unknown),Yung‐Chih Chen,(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),Shih-Chieh Chang,Yiting Li,Chun-Yao Wang	0
5	A Constructive Approach for Threshold Function Identification 2023 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown),(unknown),Yiting Li,Yung‐Chih Chen,Chun-Yao Wang	1
6	Don’t-Care-Based Logic Optimization for Threshold Logic 2023 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Yung‐Chih Chen,(unknown),(unknown)	0
7	LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),(unknown),(unknown),Chia-Chun Lin,Yung‐Chih Chen,Chun-Yao Wang	10
8	Majority Logic Circuit Minimization Using Node Addition and Removal 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Chia-Chun Lin,Yung‐Chih Chen,Chun-Yao Wang	2
9	Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chia-Chun Lin,(unknown),(unknown),Yung‐Chih Chen,Chun-Yao Wang	2
10	Dynamic Workload Allocation for Edge Computing 2021 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Yung‐Chih Chen,(unknown),(unknown),Shih-Chieh Chang	11
11	A New Necessary Condition for Threshold Function Identification 2020 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	6
12	LOOPLock: Logic Optimization-Based Cyclic Logic Locking 2019 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Yung‐Chih Chen,(unknown),(unknown),Chia-Chun Lin,Chun-Yao Wang	10
13	Contactless Testing for Prebond Interposers 2018 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Yung‐Chih Chen,(unknown),Shih-Chieh Chang	0
14	On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses 2018 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	23
15	Enhancements to SAT Attack 2018 ·ACM Transactions on Design Automation of Electronic Systems ·Yung‐Chih Chen	10
16	Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments 2018 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Chia-Chun Lin,Yung‐Chih Chen,(unknown),Chun-Yao Wang,Shigeru Yamashita	8
17	Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays 2017 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),(unknown),(unknown),Yung‐Chih Chen,Chun-Yao Wang,Suman Datta,Vijaykrishnan Narayanan	1
18	Using structural relations for checking combinationality of cyclic circuits 2015 ·Design, Automation, and Test in Europe ·(unknown),Yung‐Chih Chen,(unknown),(unknown),Chun-Yao Wang	0
19	Sensitization criterion for threshold logic circuits and its application 2013 ·International Conference on Computer Aided Design ·(unknown),Chun-Yao Wang,(unknown),Yung‐Chih Chen	3
20	On reconfigurable single-electron transistor arrays synthesis using reordering techniques 2013 ·Design, Automation, and Test in Europe ·(unknown),(unknown),Chun-Yao Wang,(unknown),Yung‐Chih Chen,Suman Datta,Vijaykrishnan Narayanan	11

About Yung‐Chih Chen

Yung‐Chih Chen is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics, having authored 117 papers that have together received 1.2k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (28 papers), Advanced Memory and Neural Computing (21 papers) and VLSI and Analog Circuit Testing (20 papers). The work is most often cited by research in Computer Networks and Communications (614 citations), Hardware and Architecture (121 citations) and Electrical and Electronic Engineering (820 citations). Yung‐Chih Chen has collaborated with scholars based in Taiwan, United States and Germany. Frequent co-authors include Don Towsley, Chun-Yao Wang, Erich Nahum, Yeon-sup Lim, Chih‐Lung Lin, Richard Gibbens, Ramin Khalili, Chia-Chun Lin, Tony Sun and Hao-Hua Chu. Their work appears in journals such as IEEE Journal on Selected Areas in Communications, RSC Advances and IEEE Transactions on Circuits and Systems for Video Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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