Yung‐Chih Chen

1.7k total citations
117 papers, 1.2k citations indexed

About

Yung‐Chih Chen is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, Yung‐Chih Chen has authored 117 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 87 papers in Electrical and Electronic Engineering, 31 papers in Hardware and Architecture and 21 papers in Artificial Intelligence. Recurrent topics in Yung‐Chih Chen's work include Low-power high-performance VLSI design (28 papers), Advanced Memory and Neural Computing (21 papers) and VLSI and Analog Circuit Testing (20 papers). Yung‐Chih Chen is often cited by papers focused on Low-power high-performance VLSI design (28 papers), Advanced Memory and Neural Computing (21 papers) and VLSI and Analog Circuit Testing (20 papers). Yung‐Chih Chen collaborates with scholars based in Taiwan, United States and Germany. Yung‐Chih Chen's co-authors include Don Towsley, Chun-Yao Wang, Erich Nahum, Yeon-sup Lim, Chih‐Lung Lin, Richard Gibbens, Ramin Khalili, Chia-Chun Lin, Tony Sun and Hao-Hua Chu and has published in prestigious journals such as IEEE Journal on Selected Areas in Communications, RSC Advances and IEEE Transactions on Circuits and Systems for Video Technology.

In The Last Decade

Yung‐Chih Chen

102 papers receiving 1.2k citations

Peers

Yung‐Chih Chen

EEE

CNC

CVPR

Jeffrey Draper United States

Dietmar Fey Germany

Gianluca Piccinini Italy

Naoya Onizawa Japan

Donald M. Chiarulli United States

Shi‐Chun Tsai Taiwan

Minsu Choi United States

Fabian Oboril Germany

Salvatore Pontarelli Italy

Dimin Niu United States

Jeffrey Draper United States

Yung‐Chih Chen

808 ×1.0

EEE

476 ×0.8

CNC

60 ×0.5

CVPR

424 ×3.5

140 ×1.5

Citations per year, relative to Yung‐Chih Chen Yung‐Chih Chen (= 1×) peers Jeffrey Draper

Countries citing papers authored by Yung‐Chih Chen

Since Specialization

Citations

This map shows the geographic impact of Yung‐Chih Chen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yung‐Chih Chen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yung‐Chih Chen more than expected).

Fields of papers citing papers by Yung‐Chih Chen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yung‐Chih Chen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yung‐Chih Chen. The network helps show where Yung‐Chih Chen may publish in the future.

Co-authorship network of co-authors of Yung‐Chih Chen

This figure shows the co-authorship network connecting the top 25 collaborators of Yung‐Chih Chen. A scholar is included among the top collaborators of Yung‐Chih Chen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yung‐Chih Chen. Yung‐Chih Chen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Chen, Yung‐Chih, et al.. (2025). Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage. ACM Transactions on Design Automation of Electronic Systems. 31(4). 1–18.

Li, Yiting, You-Cheng Lin, Yung‐Chih Chen, et al.. (2024). A Hybrid Approach to Reverse Engineering on Combinational Circuits. 1–2.

Li, Yiting, et al.. (2024). 9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(12). 4676–4686. 1 indexed citations

Chen, Yung‐Chih, et al.. (2024). IR drop Prediction Based on Machine Learning and Pattern Reduction. 516–519.

Li, Yiting, et al.. (2023). A Constructive Approach for Threshold Function Identification. ACM Transactions on Design Automation of Electronic Systems. 28(5). 1–19. 1 indexed citations

Chen, Yung‐Chih, et al.. (2023). Don’t-Care-Based Logic Optimization for Threshold Logic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42(9). 2980–2993.

Lin, Chia-Chun, et al.. (2021). LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(1). 29–34. 10 indexed citations

Lin, Chia-Chun, et al.. (2021). Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(3). 642–655. 2 indexed citations

Lin, Chia-Chun, et al.. (2021). Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(5). 1412–1422. 2 indexed citations

10.

Chen, Yung‐Chih, et al.. (2021). Dynamic Workload Allocation for Edge Computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(3). 519–529. 11 indexed citations

11.

Lin, Chia-Chun, et al.. (2020). A New Necessary Condition for Threshold Function Identification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(12). 5304–5308. 6 indexed citations

12.

Chen, Yung‐Chih, et al.. (2019). LOOPLock: Logic Optimization-Based Cyclic Logic Locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(10). 2178–2191. 10 indexed citations

13.

Chen, Yung‐Chih, et al.. (2018). Contactless Testing for Prebond Interposers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(6). 1005–1014.

14.

Lin, Chia-Chun, et al.. (2018). On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(12). 2842–2852. 23 indexed citations

15.

Chen, Yung‐Chih. (2018). Enhancements to SAT Attack. ACM Transactions on Design Automation of Electronic Systems. 23(4). 1–25. 10 indexed citations

16.

Lin, Chia-Chun, et al.. (2018). Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38(12). 2284–2297. 8 indexed citations

17.

Chen, Yung‐Chih, et al.. (2017). Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(4). 1477–1489. 1 indexed citations

18.

Chen, Yung‐Chih, et al.. (2015). Using structural relations for checking combinationality of cyclic circuits. Design, Automation, and Test in Europe. 325–328.

19.

Wang, Chun-Yao, et al.. (2013). Sensitization criterion for threshold logic circuits and its application. International Conference on Computer Aided Design. 226–233. 3 indexed citations

20.

Wang, Chun-Yao, et al.. (2013). On reconfigurable single-electron transistor arrays synthesis using reordering techniques. Design, Automation, and Test in Europe. 1807–1812. 11 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact