Y.S. Dhillon

415 total citations
14 papers, 289 citations indexed

About

Y.S. Dhillon is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, Y.S. Dhillon has authored 14 papers receiving a total of 289 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 1 paper in Artificial Intelligence. Recurrent topics in Y.S. Dhillon's work include Low-power high-performance VLSI design (14 papers), Radiation Effects in Electronics (7 papers) and VLSI and FPGA Design Techniques (5 papers). Y.S. Dhillon is often cited by papers focused on Low-power high-performance VLSI design (14 papers), Radiation Effects in Electronics (7 papers) and VLSI and FPGA Design Techniques (5 papers). Y.S. Dhillon collaborates with scholars based in United States and Italy. Y.S. Dhillon's co-authors include A.U. Diril, Abhijit Chatterjee, A.D. Singh, Hsien-Hsin S. Lee, Cecilia Metra and Adit D. Singh and has published in prestigious journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Journal of Low Power Electronics and International Conference on Computer Aided Design.

In The Last Decade

Y.S. Dhillon

14 papers receiving 275 citations

Peers

Countries citing papers authored by Y.S. Dhillon

Since Specialization

Citations

This map shows the geographic impact of Y.S. Dhillon's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y.S. Dhillon with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y.S. Dhillon more than expected).

Fields of papers citing papers by Y.S. Dhillon

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y.S. Dhillon. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y.S. Dhillon. The network helps show where Y.S. Dhillon may publish in the future.

Co-authorship network of co-authors of Y.S. Dhillon

This figure shows the co-authorship network connecting the top 25 collaborators of Y.S. Dhillon. A scholar is included among the top collaborators of Y.S. Dhillon based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y.S. Dhillon. Y.S. Dhillon is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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14 of 14 papers shown

#	Work	Indexed citations
1	Analysis and optimization of nanometer CMOS circuits for soft-error tolerance 2006 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, A.D. Singh	69
2	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance 2005 ·A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, A.D. Singh	16
3	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages 2005 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, A.D. Singh	22
4	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages 2005 ·A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, A.D. Singh	9
5	Low-power domino circuits using NMOS pull-up on off-critical paths 2005 ·A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, Adit D. Singh	2
6	Pseudo Dual Supply Voltage Domino Logic Design 2005 ·Journal of Low Power Electronics ·A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, Adit D. Singh	1
7	Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits 2005 ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, Cecilia Metra	14
8	Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits 2005 ·Design, Automation, and Test in Europe ·Y.S. Dhillon, A.U. Diril, (unknown)	96
9	Sizing CMOS circuits for increased transient error tolerance 2004 ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, A.D. Singh	12
10	Sizing CMOS circuits for increased transient error tolerance 2004 ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, (unknown)	10
11	Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level 2004 ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee	10
12	Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level 2003 ·International Conference on Computer Aided Design ·Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee	20
13	An O(N) supply voltage assignment algorithm for low-energy serially connected CMOS modules and a heuristic extension to acyclic data flow graphs 2003 ·A.U. Diril, Y.S. Dhillon, (unknown), Abhijit Chatterjee	4
14	The Elusive Metric for Low-Power Architecture Research 2003 ·Hsien-Hsin S. Lee, (unknown), A.U. Diril, Y.S. Dhillon	4

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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