Adit D. Singh

944 total citations
73 papers, 646 citations indexed

About

Adit D. Singh is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Cellular and Molecular Neuroscience. According to data from OpenAlex, Adit D. Singh has authored 73 papers receiving a total of 646 indexed citations (citations by other indexed papers that have themselves been cited), including 71 papers in Electrical and Electronic Engineering, 63 papers in Hardware and Architecture and 7 papers in Cellular and Molecular Neuroscience. Recurrent topics in Adit D. Singh's work include Integrated Circuits and Semiconductor Failure Analysis (50 papers), VLSI and Analog Circuit Testing (49 papers) and Low-power high-performance VLSI design (20 papers). Adit D. Singh is often cited by papers focused on Integrated Circuits and Semiconductor Failure Analysis (50 papers), VLSI and Analog Circuit Testing (49 papers) and Low-power high-performance VLSI design (20 papers). Adit D. Singh collaborates with scholars based in United States, India and Germany. Adit D. Singh's co-authors include Ujjwal Guin, Chao Han, Ziqi Zhou, Virendra Singh, Abhijit Chatterjee, Sreejit Chakravarty, Wendong Wang, Hee Yong Youn, Anthony Skjellum and Mahabubul Alam and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Adit D. Singh

69 papers receiving 630 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Adit D. Singh United States	17	532	522	72	60	59	73	646
John M. Acken United States	12	426 0.8×	435 0.8×	54 0.8×	19 0.3×	82 1.4×	57	608
Raj Gautam Dutta United States	13	254 0.5×	194 0.4×	161 2.2×	54 0.9×	67 1.1×	25	419
Luca Cassano Italy	11	234 0.4×	290 0.6×	85 1.2×	19 0.3×	55 0.9×	64	405
Fareena Saqib United States	11	361 0.7×	271 0.5×	216 3.0×	76 1.3×	97 1.6×	51	556
Nikolaos Athanasios Anagnostopoulos Germany	12	202 0.4×	191 0.4×	76 1.1×	47 0.8×	78 1.3×	48	327
Azadeh Davoodi United States	18	596 1.1×	751 1.4×	71 1.0×	43 0.7×	146 2.5×	109	860
Kurt Rosenfeld United States	7	579 1.1×	445 0.9×	186 2.6×	226 3.8×	33 0.6×	10	683
Emmanouil Kalligeros Greece	15	436 0.8×	435 0.8×	64 0.9×	19 0.3×	85 1.4×	39	546
Masaya Yoshikawa Japan	9	190 0.4×	154 0.3×	164 2.3×	45 0.8×	40 0.7×	113	338
Md Tanvir Arafin United States	10	110 0.2×	177 0.3×	85 1.2×	30 0.5×	74 1.3×	25	298

Countries citing papers authored by Adit D. Singh

Since Specialization

Citations

This map shows the geographic impact of Adit D. Singh's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Adit D. Singh with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Adit D. Singh more than expected).

Fields of papers citing papers by Adit D. Singh

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Adit D. Singh. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Adit D. Singh. The network helps show where Adit D. Singh may publish in the future.

Co-authorship network of co-authors of Adit D. Singh

This figure shows the co-authorship network connecting the top 25 collaborators of Adit D. Singh. A scholar is included among the top collaborators of Adit D. Singh based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Adit D. Singh. Adit D. Singh is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Singh, Adit D.. (2024). Silent Data Corruption from Timing Marginalities Due to Process Variations. 1–7.

Guin, Ujjwal, et al.. (2019). Two-Pattern ∆IDDQ Test for Recycled IC Detection. 82–87. 5 indexed citations

Guin, Ujjwal, et al.. (2018). A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. 85–90. 30 indexed citations

Reddy, S.M., et al.. (2017). Efficient SAT-based generation of hazard-activated TSOF tests. 1–6. 1 indexed citations

Singh, Adit D.. (2016). Adaptive Test Methods for High IC Quality and Reliability. 21–22.

Wang, Yu & Adit D. Singh. (2015). An Efficient Transition Detector Exploiting Charge Sharing. 298–303. 1 indexed citations

Singh, Adit D., et al.. (2014). High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. 200–205. 4 indexed citations

Singh, Virendra, et al.. (2011). SSTKR: Secure and Testable Scan Design through Test Key Randomization. 60–65. 28 indexed citations

Han, Chao, Adit D. Singh, & Virendra Singh. (2011). Efficient partial enhanced scan for high coverage delay testing. 243–248. 2 indexed citations

10.

Singh, Adit D., et al.. (2010). Current Sensing Completion Detection for high speed and area efficient arithmetic. 7. 240–243. 4 indexed citations

11.

Singh, Abhishek, P. A. Khan, Virendra Singh, Kewal K. Saluja, & Adit D. Singh. (2010). Test application time minimization for RAS using basis optimization of column decoder. 2614–2617. 2 indexed citations

12.

Mishra, Amit Kumar, et al.. (2010). Modified Scan Flip-Flop for Low Power Testing. 367–370. 17 indexed citations

13.

Larsson, Erik, et al.. (2009). Capture Power Reduction for Modular System-on-Chip Test. NOT FOUND REPOSITORY (Indian Institute of Science Bangalore). 1 indexed citations

14.

Singh, Virendra, et al.. (2009). Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. 237–240. 3 indexed citations

15.

Ashouei, Maryam, et al.. (2009). Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18(4). 675–679. 2 indexed citations

16.

Ashouei, Maryam, et al.. (2007). Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. 711–716. 4 indexed citations

17.

Singh, Adit D., et al.. (2007). Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. 335–340. 8 indexed citations

18.

Youn, Hee Yong & Adit D. Singh. (1989). A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI.. Proceedings of the International Conference on Parallel Processing. 2012. 261–265. 6 indexed citations

19.

Youn, Hee Yong & Adit D. Singh. (1988). A Highly Efficient Design for Reconfiguring the Processor Array in VLSI.. Proceedings of the International Conference on Parallel Processing. 375–382. 8 indexed citations

20.

Singh, Adit D. & James R. Armstrong. (1978). A simultaneous, radix four, I2L multiplier mechanized via repeated addition. 114–121. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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