Young-Chul Cho

422 total citations
23 papers, 198 citations indexed

About

Young-Chul Cho is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Young-Chul Cho has authored 23 papers receiving a total of 198 indexed citations (citations by other indexed papers that have themselves been cited), including 11 papers in Hardware and Architecture, 9 papers in Computer Networks and Communications and 8 papers in Electrical and Electronic Engineering. Recurrent topics in Young-Chul Cho's work include Embedded Systems Design Techniques (9 papers), Parallel Computing and Optimization Techniques (9 papers) and Interconnection Networks and Systems (8 papers). Young-Chul Cho is often cited by papers focused on Embedded Systems Design Techniques (9 papers), Parallel Computing and Optimization Techniques (9 papers) and Interconnection Networks and Systems (8 papers). Young-Chul Cho collaborates with scholars based in South Korea, France and United States. Young-Chul Cho's co-authors include Joo Sun Choi, Seong-Jin Jang, Ki‐Young Choi, Sungjoo Yoo, Jae‐Yoon Sim, Hong-June Park, Youngwoo Ji, Jong Mi Lee, Byungsub Kim and Nacer-Eddine Zergainoh and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Journal of the Korean Ceramic Society and Design Automation for Embedded Systems.

In The Last Decade

Young-Chul Cho

15 papers receiving 192 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Young-Chul Cho South Korea 7 130 77 68 59 9 23 198
Gordon Gammie United States 8 248 1.9× 60 0.8× 94 1.4× 29 0.5× 17 283
Alan Smith United States 8 133 1.0× 17 0.2× 95 1.4× 118 2.0× 19 236
Nobukazu Takai Japan 10 291 2.2× 184 2.4× 63 0.9× 34 0.6× 65 310
Michael Sperling United States 8 234 1.8× 81 1.1× 83 1.2× 27 0.5× 11 258
A. Ho United States 7 415 3.2× 111 1.4× 81 1.2× 41 0.7× 8 422
Naohiko Irie Japan 9 200 1.5× 41 0.5× 79 1.2× 63 1.1× 18 254
T.P. Thrush United States 8 319 2.5× 72 0.9× 61 0.9× 46 0.8× 8 330
Kiyoo Itoh Japan 8 268 2.1× 22 0.3× 89 1.3× 57 1.0× 29 294
Yoichi Koyanagi Japan 11 390 3.0× 49 0.6× 77 1.1× 53 0.9× 27 421
P. Parries United States 10 230 1.8× 19 0.2× 114 1.7× 95 1.6× 19 273

Countries citing papers authored by Young-Chul Cho

Since Specialization
Citations

This map shows the geographic impact of Young-Chul Cho's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Young-Chul Cho with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Young-Chul Cho more than expected).

Fields of papers citing papers by Young-Chul Cho

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Young-Chul Cho. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Young-Chul Cho. The network helps show where Young-Chul Cho may publish in the future.

Co-authorship network of co-authors of Young-Chul Cho

This figure shows the co-authorship network connecting the top 25 collaborators of Young-Chul Cho. A scholar is included among the top collaborators of Young-Chul Cho based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Young-Chul Cho. Young-Chul Cho is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Yoon, Sung‐Jin, Man‐Ho Lee, Kwangho Kim, et al.. (2024). Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6. 1–3.
5.
Park, Jae‐Woo, Hyunyoon Cho, Youngmin Kim, et al.. (2021). A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. 463–466. 6 indexed citations
6.
Egger, Bernhard, Hochan Lee, Young-Chul Cho, et al.. (2017). A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures. 197–209. 6 indexed citations
7.
Egger, Bernhard, Hochan Lee, Young-Chul Cho, et al.. (2017). A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures. 197–209. 7 indexed citations
8.
Yi, Il-Min, Seung-Jun Bae, Young-Chul Cho, et al.. (2016). A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. 1–2. 2 indexed citations
9.
Lee, Dong Kun, et al.. (2015). An Analysis of the water balance of Low Impact Development Techniques According to the Rainfall Types. Journal of Environmental Impact Assessment. 24(2). 163–174.
10.
Lee, Jong Mi, Youngwoo Ji, Young-Chul Cho, et al.. (2015). 5.7 A 29nW bandgap reference circuit. 1–3. 74 indexed citations
11.
Chung, Hoeju, Kiwon Lee, Seung-Hoon Oh, et al.. (2014). A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. IEEE Journal of Solid-State Circuits. 50(1). 178–190. 40 indexed citations
12.
Cho, Young-Chul, Minho Park, Youngjin Jeon, et al.. (2013). A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application. 11 indexed citations
13.
Cho, Young-Chul, Nacer-Eddine Zergainoh, Ki‐Young Choi, & Ahmed Jerraya. (2007). Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. SPIRE - Sciences Po Institutional REpository. 195–201. 2 indexed citations
14.
Cho, Young-Chul, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Jerraya, & Ki‐Young Choi. (2007). Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Design Automation for Embedded Systems. 11(2-3). 167–191. 7 indexed citations
15.
Cho, Young-Chul, Sungjoo Yoo, Ki‐Young Choi, Nacer-Eddine Zergainoh, & Ahmed Jerraya. (2005). Scheduler implementation in MP SoC design. 151–151. 20 indexed citations
16.
Cho, Young-Chul, et al.. (2005). Scheduling and iming analysis of HW/SW on-chip communication in MP SoC design. 2003 Design, Automation and Test in Europe Conference and Exhibition. 132–137. 1 indexed citations
17.
Cho, Young-Chul, et al.. (2005). Scheduler implementation in MP SoC design. SPIRE - Sciences Po Institutional REpository. 1. 151–156. 6 indexed citations
18.
Cho, Young-Chul, et al.. (2003). Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design. 2003 Design, Automation and Test in Europe Conference and Exhibition. 132–137. 3 indexed citations
19.
Yoo, Sungjoo, et al.. (2000). Fast hardware-software coverification by optimistic execution of real processor. 663–668. 2 indexed citations
20.
Yoo, Sungjoo, et al.. (2000). Performance estimation of multiple-cache IP-based systems. 77–81.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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