Hyunyoon Cho

540 total citations
9 papers, 165 citations indexed

About

Hyunyoon Cho is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Hyunyoon Cho has authored 9 papers receiving a total of 165 indexed citations (citations by other indexed papers that have themselves been cited), including 6 papers in Hardware and Architecture, 5 papers in Electrical and Electronic Engineering and 4 papers in Computer Networks and Communications. Recurrent topics in Hyunyoon Cho's work include Parallel Computing and Optimization Techniques (4 papers), Semiconductor materials and devices (4 papers) and Advanced Data Storage Technologies (4 papers). Hyunyoon Cho is often cited by papers focused on Parallel Computing and Optimization Techniques (4 papers), Semiconductor materials and devices (4 papers) and Advanced Data Storage Technologies (4 papers). Hyunyoon Cho collaborates with scholars based in South Korea and United States. Hyunyoon Cho's co-authors include Young Hoon Son, Jung Ho Ahn, Nam Sung Kim, Yuhwan Ro, Joo Sun Choi, O Seongil, Hyunsung Shin, Kwang‐Il Park, Sukhan Lee and Jung-Bae Lee and has published in prestigious journals such as IEEE Access and IEEE Computer Architecture Letters.

In The Last Decade

Hyunyoon Cho

9 papers receiving 162 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Hyunyoon Cho South Korea 7 117 90 71 9 8 9 165
Zied Marrakchi France 7 134 1.1× 97 1.1× 45 0.6× 14 1.6× 7 0.9× 31 163
R. Rand United States 7 83 0.7× 53 0.6× 48 0.7× 12 1.3× 7 0.9× 11 133
Robert Giterman Israel 11 367 3.1× 103 1.1× 56 0.8× 10 1.1× 3 0.4× 36 390
Matthias Függer Austria 9 78 0.7× 99 1.1× 87 1.2× 14 1.6× 3 0.4× 38 172
Nacer-Eddine Zergainoh France 9 95 0.8× 125 1.4× 153 2.2× 8 0.9× 3 0.4× 31 216
D.R. Donchin United States 6 140 1.2× 163 1.8× 102 1.4× 8 0.9× 4 0.5× 8 213
Leomar S. da Rosa Brazil 9 243 2.1× 115 1.3× 40 0.6× 7 0.8× 6 0.8× 56 273
Anish Muttreja United States 8 186 1.6× 73 0.8× 51 0.7× 9 1.0× 7 0.9× 12 227
C. Lane United States 4 145 1.2× 129 1.4× 45 0.6× 3 0.3× 4 0.5× 10 176
Timothy N. Miller United States 7 142 1.2× 149 1.7× 83 1.2× 7 0.8× 2 0.3× 18 199

Countries citing papers authored by Hyunyoon Cho

Since Specialization
Citations

This map shows the geographic impact of Hyunyoon Cho's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Hyunyoon Cho with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Hyunyoon Cho more than expected).

Fields of papers citing papers by Hyunyoon Cho

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Hyunyoon Cho. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Hyunyoon Cho. The network helps show where Hyunyoon Cho may publish in the future.

Co-authorship network of co-authors of Hyunyoon Cho

This figure shows the co-authorship network connecting the top 25 collaborators of Hyunyoon Cho. A scholar is included among the top collaborators of Hyunyoon Cho based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Hyunyoon Cho. Hyunyoon Cho is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

9 of 9 papers shown
1.
Park, Jae‐Woo, Hyunyoon Cho, Youngmin Kim, et al.. (2021). A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. 463–466. 6 indexed citations
2.
Cho, Hyunyoon, Jin‐Hee Park, Kyoung-Soo Kim, et al.. (2021). A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. 1–3. 6 indexed citations
3.
Lee, Sukhan, Hyunyoon Cho, Young Hoon Son, et al.. (2018). Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. IEEE Access. 6. 31387–31398. 21 indexed citations
4.
Seongil, O, Hyunsung Shin, Kwang‐Il Park, et al.. (2017). Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. 61–72. 58 indexed citations
5.
Lee, Sukhan, Yuhwan Ro, Young Hoon Son, et al.. (2017). Understanding power-performance relationship of energy-efficient modern DRAM devices. 110–111. 4 indexed citations
6.
Ro, Yuhwan, Hyunyoon Cho, Eojin Lee, et al.. (2017). SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. 517–528. 6 indexed citations
7.
Son, Young Hoon, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, & Jung Ho Ahn. (2016). SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. IEEE Computer Architecture Letters. 16(1). 76–79. 5 indexed citations
8.
Park, Joon-Young, et al.. (2012). A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. 44–46. 29 indexed citations
9.
Lee, Hocheol, Donghyuk Lee, Jin-Guk Kim, et al.. (2011). 28.5 A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-Based Stacking. 30 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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