Naohiko Irie

417 total citations
18 papers, 254 citations indexed

About

Naohiko Irie is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Naohiko Irie has authored 18 papers receiving a total of 254 indexed citations (citations by other indexed papers that have themselves been cited), including 11 papers in Electrical and Electronic Engineering, 10 papers in Hardware and Architecture and 6 papers in Computer Networks and Communications. Recurrent topics in Naohiko Irie's work include Parallel Computing and Optimization Techniques (7 papers), 3D IC and TSV technologies (6 papers) and Interconnection Networks and Systems (5 papers). Naohiko Irie is often cited by papers focused on Parallel Computing and Optimization Techniques (7 papers), 3D IC and TSV technologies (6 papers) and Interconnection Networks and Systems (5 papers). Naohiko Irie collaborates with scholars based in Japan and United States. Naohiko Irie's co-authors include Toshihiro Hattori, Tadahiro Kuroda, Kiichi Niitsu, Kenichi Osada, Atsushi Hasegawa, Yuichi Shimazaki, Takahiro Irita, Hiroki Ishikuro, Hiroyuki Mizuno and Yasuhisa Shimazaki and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Micro.

In The Last Decade

Naohiko Irie

18 papers receiving 251 citations

Peers

Countries citing papers authored by Naohiko Irie

Since Specialization

Citations

This map shows the geographic impact of Naohiko Irie's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Naohiko Irie with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Naohiko Irie more than expected).

Fields of papers citing papers by Naohiko Irie

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Naohiko Irie. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Naohiko Irie. The network helps show where Naohiko Irie may publish in the future.

Co-authorship network of co-authors of Naohiko Irie

This figure shows the co-authorship network connecting the top 25 collaborators of Naohiko Irie. A scholar is included among the top collaborators of Naohiko Irie based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Naohiko Irie. Naohiko Irie is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

#	Work	Indexed citations
1	3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link 2010 ·IEEE Journal of Solid-State Circuits ·(unknown), Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, (unknown), (unknown), (unknown), (unknown), Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda	21
2	Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration 2010 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Kiichi Niitsu, (unknown), (unknown), Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda	8
3	Domain Partitioning Technology for Embedded Multicore Processors 2009 ·IEEE Micro ·(unknown), Yuki Kondo, Naohiko Irie, Masayuki Itô, Hajime Sasaki, (unknown)	8
4	Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration 2009 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Kiichi Niitsu, (unknown), (unknown), (unknown), Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda	12
5	An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM 2009 ·Kiichi Niitsu, Yuichi Shimazaki, (unknown), Yasuaki Kohama, (unknown), (unknown), (unknown), Setsuko Komatsu, Kensuke Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda	46
6	3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links 2009 ·Kenichi Osada, (unknown), Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, (unknown), (unknown), (unknown), (unknown), Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda	8
7	Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for 3D System Integration 2008 ·Kiichi Niitsu, Yasuaki Kohama, (unknown), Kensuke Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda	5
8	Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs 2007 ·IEEE Journal of Solid-State Circuits ·(unknown), Hiroyuki Mizuno, (unknown), Kei Hirose, Yasuhisa Shimazaki, (unknown), (unknown), (unknown), Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie	31
9	Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor 2007 ·(unknown), Hiroyuki Mizuno, (unknown), Kei Hirose, Yasuhisa Shimazaki, (unknown), (unknown), (unknown), Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie	3
10	A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption 2007 ·Yutaka Yoshida, T. Kamei, (unknown), (unknown), (unknown), Toshihiro Hattori, Atsushi Hasegawa, (unknown), Naohiko Irie, Kunio Uchiyama, (unknown), (unknown), Keiji Kimura, Hironori Kasahara	17
11	A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core 2007 ·IEICE Transactions on Electronics ·Tetsuya Yamada, Naohiko Irie, Toshiyuki Tsunoda, Takahiro Irita, (unknown), Reiko Yoshida, Keisuke Toyama, (unknown)	1
12	Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link 2007 ·Kiichi Niitsu, (unknown), (unknown), Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda	21
13	Performance and power evaluation of SH-X3 multicore system 2007 ·(unknown), (unknown), (unknown), T. Kamei, Yutaka Yoshida, (unknown), Naohiko Irie, (unknown), Toshihiro Hattori	1
14	Embedded SoC Resource Manager to Control Temperature and Data Bandwidth 2007 ·(unknown), Kenichi Osada, (unknown), (unknown), (unknown), (unknown), T. Kamei, Yutaka Yoshida, (unknown), (unknown), Takayasu Ito, (unknown), Naohiko Irie	9
15	Elastic shared resource scheduling SOC interconnect architecture for real-time system 2006 ·(unknown), Hiroki Ueda, (unknown), Eiji Yamamoto, (unknown), (unknown), Yuki Kondo, (unknown), (unknown), Naohiko Irie, (unknown)	2
16	Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor 2006 ·(unknown), Hiroyuki Mizuno, (unknown), Kenzo Hirose, Yuichi Shimazaki, (unknown), (unknown), Toshiaki Ishii, (unknown), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie	32
17	A resume-standby application processor for 3G cellular phones 2004 ·T. Kamei, Masatoshi Ishikawa, (unknown), Takahiro Irita, Minoru Abe, (unknown), (unknown), (unknown), (unknown), S. Tamaki, (unknown), Yuichi Shimazaki, (unknown), Hiroyuki Mizuno, Naohiko Irie, (unknown), (unknown), Kenzo Hirose, Shinichi Yoshioka, Toshihiro Hattori	27
18	Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products 2001 ·IEICE Transactions on Electronics ·Kunio Uchiyama, (unknown), Yasuhiko Saito, (unknown), Atsushi Hasegawa, Shinichi Yoshioka, Naohiko Irie, Takeshi Kitahara, (unknown), (unknown)	2

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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