J. Leenstra

1.2k total citations
25 papers, 717 citations indexed

About

J. Leenstra is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, J. Leenstra has authored 25 papers receiving a total of 717 indexed citations (citations by other indexed papers that have themselves been cited), including 22 papers in Hardware and Architecture, 19 papers in Electrical and Electronic Engineering and 4 papers in Computer Networks and Communications. Recurrent topics in J. Leenstra's work include Parallel Computing and Optimization Techniques (11 papers), VLSI and Analog Circuit Testing (11 papers) and Integrated Circuits and Semiconductor Failure Analysis (8 papers). J. Leenstra is often cited by papers focused on Parallel Computing and Optimization Techniques (11 papers), VLSI and Analog Circuit Testing (11 papers) and Integrated Circuits and Semiconductor Failure Analysis (8 papers). J. Leenstra collaborates with scholars based in Germany, United States and Netherlands. J. Leenstra's co-authors include Hans-Joachim Wunderlich, Christian G. Zoellin, Silvia Melitta Mueller, Balaram Sinharoy, H. Q. Le, Ronald Barber, D R Sharpe, Sam Lightstone, Vijayshankar Raman and Rene Mueller and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IBM Journal of Research and Development and Proceedings of the VLDB Endowment.

In The Last Decade

J. Leenstra

22 papers receiving 661 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
J. Leenstra Germany 11 438 365 297 125 104 25 717
K. Scott Hemmert United States 15 647 1.5× 501 1.4× 280 0.9× 116 0.9× 76 0.7× 39 902
Sergio López-Buedo Spain 15 371 0.8× 430 1.2× 382 1.3× 170 1.4× 32 0.3× 56 791
Zvonimir Rakamarić United States 14 400 0.9× 299 0.8× 156 0.5× 107 0.9× 101 1.0× 42 705
Alastair Reid United States 15 446 1.0× 345 0.9× 119 0.4× 98 0.8× 63 0.6× 29 755
Ju-Wook Jang South Korea 11 177 0.4× 200 0.5× 180 0.6× 81 0.6× 38 0.4× 33 418
Yu Cai United States 12 287 0.7× 805 2.2× 278 0.9× 136 1.1× 40 0.4× 32 949
P. Banerjee United States 18 682 1.6× 671 1.8× 221 0.7× 42 0.3× 25 0.2× 69 910
Abhishek Das India 10 371 0.8× 334 0.9× 77 0.3× 52 0.4× 34 0.3× 28 627
Gordon Brebner United States 13 564 1.3× 945 2.6× 311 1.0× 90 0.7× 21 0.2× 42 1.1k
Wei‐Chung Hsu Taiwan 18 992 2.3× 763 2.1× 160 0.5× 221 1.8× 48 0.5× 123 1.1k

Countries citing papers authored by J. Leenstra

Since Specialization
Citations

This map shows the geographic impact of J. Leenstra's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Leenstra with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Leenstra more than expected).

Fields of papers citing papers by J. Leenstra

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Leenstra. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Leenstra. The network helps show where J. Leenstra may publish in the future.

Co-authorship network of co-authors of J. Leenstra

This figure shows the co-authorship network connecting the top 25 collaborators of J. Leenstra. A scholar is included among the top collaborators of J. Leenstra based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Leenstra. J. Leenstra is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Sinharoy, Balaram, Richard J. Eickemeyer, H. Q. Le, et al.. (2015). IBM POWER8 processor core microarchitecture. IBM Journal of Research and Development. 59(1). 2:1–2:21. 84 indexed citations
2.
Ziegler, Matthew M., Ruchir Puri, R. Franch, et al.. (2014). POWER8 design methodology innovations for improving productivity and reducing power. 1–9. 8 indexed citations
3.
Raman, Vijayshankar, Ronald Barber, J. Leenstra, et al.. (2013). DB2 with BLU acceleration. Proceedings of the VLDB Endowment. 6(11). 1080–1091. 182 indexed citations
4.
Sinharoy, Balaram, R. Kalla, William J. Starke, et al.. (2011). IBM POWER7 multicore server processor. IBM Journal of Research and Development. 55(3). 1:1–1:29. 108 indexed citations
5.
Friedrich, Joshua, et al.. (2010). The power7<sup>TM</sup> processor SoC. 71–73. 2 indexed citations
6.
Wunderlich, Hans-Joachim, et al.. (2008). Scan chain clustering for test power reduction. Fachbereich Informatik (University of Stuttgart). 828–833. 20 indexed citations
7.
Leenstra, J., et al.. (2007). IBM POWER6 accelerators: VMX and DFU. IBM Journal of Research and Development. 51(6). 1–21. 74 indexed citations
8.
Zoellin, Christian G., et al.. (2007). Scan test planning for power reduction. Proceedings - ACM IEEE Design Automation Conference. 521–521. 13 indexed citations
9.
Zoellin, Christian G., et al.. (2006). BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Fachbereich Informatik (University of Stuttgart). 1–8. 39 indexed citations
10.
11.
Flachs, B., S. Asano, S.H. Dhong, et al.. (2005). A streaming processing unit for a CELL processor. 134–135. 93 indexed citations
12.
13.
Leenstra, J. & Lambert Spaanenburg. (2005). Hierarchical Test Program Development for Scan Testable Circuits. 375–375.
14.
Leenstra, J., et al.. (2003). Issues in the test of artificial neural networks. 487–490.
15.
Leenstra, J., et al.. (2002). A 1.8 GHz Instruction Window Buffer. 314–315,. 6 indexed citations
16.
Leenstra, J. & Lambert Spaanenburg. (2002). Hierarchical test assembly for macro based VLSI design. 520–529. 9 indexed citations
17.
Leenstra, J., et al.. (2002). On scan path design for stuck-open and delay fault detection. 201–210. 11 indexed citations
18.
Kessler, Mathieu, et al.. (2002). Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. Fachbereich Informatik (University of Stuttgart). c 23. 461–469. 3 indexed citations
19.
Leenstra, J., et al.. (2001). A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. IEEE Journal of Solid-State Circuits. 36(11). 1628–1635. 9 indexed citations
20.
Allen, D.H., S.H. Dhong, H. Peter Hofstee, et al.. (2000). Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development. 44(6). 799–822. 24 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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