Rung‐Bin Lin

502 total citations
75 papers, 355 citations indexed

About

Rung‐Bin Lin is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Rung‐Bin Lin has authored 75 papers receiving a total of 355 indexed citations (citations by other indexed papers that have themselves been cited), including 66 papers in Electrical and Electronic Engineering, 43 papers in Hardware and Architecture and 17 papers in Computer Networks and Communications. Recurrent topics in Rung‐Bin Lin's work include VLSI and FPGA Design Techniques (49 papers), VLSI and Analog Circuit Testing (37 papers) and Low-power high-performance VLSI design (26 papers). Rung‐Bin Lin is often cited by papers focused on VLSI and FPGA Design Techniques (49 papers), VLSI and Analog Circuit Testing (37 papers) and Low-power high-performance VLSI design (26 papers). Rung‐Bin Lin collaborates with scholars based in Taiwan, United States and Japan. Rung‐Bin Lin's co-authors include Myungchul Kim, Chi‐Ming Tsai, Shih-Hsu Huang, Eugene Shragowitz, Yih-Lang Li, Shuyu Chen, Shigetoshi Nakatake, Jianyang Zhou, Chi‐Hung Lin and Chih-Chun Hsu and has published in prestigious journals such as Information Sciences, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Annals of Operations Research.

In The Last Decade

Rung‐Bin Lin

64 papers receiving 340 citations

Peers

Rung‐Bin Lin
M. d'Abreu United States
Ilgweon Kang United States
Gustavo Tèllez United States
Yuejian Wu Canada
Mahesh A. Iyer United States
H. Guzmán-Miranda Spain
Ulrich Lauther Germany
H.T. Vierhaus Germany
Eric Felt United States
P. Kozak United States
M. d'Abreu United States
Rung‐Bin Lin
Citations per year, relative to Rung‐Bin Lin Rung‐Bin Lin (= 1×) peers M. d'Abreu

Countries citing papers authored by Rung‐Bin Lin

Since Specialization
Citations

This map shows the geographic impact of Rung‐Bin Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Rung‐Bin Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Rung‐Bin Lin more than expected).

Fields of papers citing papers by Rung‐Bin Lin

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Rung‐Bin Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Rung‐Bin Lin. The network helps show where Rung‐Bin Lin may publish in the future.

Co-authorship network of co-authors of Rung‐Bin Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Rung‐Bin Lin. A scholar is included among the top collaborators of Rung‐Bin Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Rung‐Bin Lin. Rung‐Bin Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
3.
Lin, Rung‐Bin, et al.. (2019). Impact of Double-Row Height Standard Cells on Placement and Routing. 317–322. 6 indexed citations
4.
Chiang, Yu‐Cheng, et al.. (2018). Recognition of regular layout structures. 75–81.
5.
Kim, Myungchul, Shih-Hsu Huang, Rung‐Bin Lin, & Shigetoshi Nakatake. (2017). Overview of the 2017 CAD contest at ICCAD. International Conference on Computer Aided Design. 855–856. 1 indexed citations
6.
Lin, Chi‐Hung, et al.. (2016). Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. 673–678. 2 indexed citations
7.
Lu, Ang, et al.. (2015). Simultaneous transistor pairing and placement for CMOS standard cells. Design, Automation, and Test in Europe. 1647–1652. 7 indexed citations
8.
Natarajan, V., Shih-Hsu Huang, Rung‐Bin Lin, & Myungchul Kim. (2015). Overview of the 2015 CAD Contest at ICCAD. 910–911. 4 indexed citations
9.
Lin, Rung‐Bin, et al.. (2013). Slack budgeting and slack to length converting for multi-bit flip-flop merging. Design, Automation, and Test in Europe. 1837–1842. 1 indexed citations
10.
Lin, Rung‐Bin, et al.. (2012). Design and analysis of via-configurable routing fabrics for structured ASICs. Design, Automation, and Test in Europe. 1479–1482. 1 indexed citations
11.
Lin, Rung‐Bin, et al.. (2010). Power gating design for standard-cell-like structured ASICs. Design, Automation, and Test in Europe. 514–519. 11 indexed citations
12.
Lin, Rung‐Bin, et al.. (2010). Power gating design for standard-cell-like structured ASICs. 514–519. 8 indexed citations
13.
Chen, Yu–Chen, et al.. (2009). Via-configurable logic block architectures for standard cell like structured ASICs. 17–20. 2 indexed citations
14.
Lin, Rung‐Bin, et al.. (2009). Using structured ASIC to improve design productivity. 25–28. 2 indexed citations
15.
Lin, Rung‐Bin, et al.. (2008). Chip placement in a reticle for multiple-project wafer fabrication. ACM Transactions on Design Automation of Electronic Systems. 13(1). 1–21. 6 indexed citations
16.
Lin, Tsung-Han, et al.. (2007). Double-via-driven standard cell library design. Design, Automation, and Test in Europe. 1212–1217. 7 indexed citations
17.
Lin, Rung‐Bin, et al.. (2006). Is more redundancy better for on-chip bus encoding. 4–4. 1 indexed citations
18.
Lin, Rung‐Bin, et al.. (2005). Multiple Project Wafers for Medium-Volume IC Production. 4725–4728. 7 indexed citations
19.
Lin, Rung‐Bin & Chi‐Ming Tsai. (2002). Weight-Based Bus-Invert Coding for Low-Power Applications. Asia and South Pacific Design Automation Conference. 121–125. 5 indexed citations
20.
Lin, Rung‐Bin, et al.. (1991). Bounds on Net Delays for Physical Design of Fast Circuits.. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 111–118.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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