Rakesh Patel

1.1k total citations
17 papers, 321 citations indexed

About

Rakesh Patel is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Rakesh Patel has authored 17 papers receiving a total of 321 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 10 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in Rakesh Patel's work include VLSI and Analog Circuit Testing (6 papers), Low-power high-performance VLSI design (6 papers) and Advancements in PLL and VCO Technologies (5 papers). Rakesh Patel is often cited by papers focused on VLSI and Analog Circuit Testing (6 papers), Low-power high-performance VLSI design (6 papers) and Advancements in PLL and VCO Technologies (5 papers). Rakesh Patel collaborates with scholars based in United States and Netherlands. Rakesh Patel's co-authors include Vivek Tiwari, Suresh Rajgopal, Gaurav Mehta, Lawrence T. Clark, Sergey Shumarayev, Changhee Lee, T. Kwaśniewski, Bruce Pedersen, P. S. Plekhanov and Conor Puls and has published in prestigious journals such as PubMed.

In The Last Decade

Rakesh Patel

16 papers receiving 286 citations

Peers

Countries citing papers authored by Rakesh Patel

Since Specialization

Citations

This map shows the geographic impact of Rakesh Patel's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Rakesh Patel with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Rakesh Patel more than expected).

Fields of papers citing papers by Rakesh Patel

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Rakesh Patel. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Rakesh Patel. The network helps show where Rakesh Patel may publish in the future.

Co-authorship network of co-authors of Rakesh Patel

This figure shows the co-authorship network connecting the top 25 collaborators of Rakesh Patel. A scholar is included among the top collaborators of Rakesh Patel based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Rakesh Patel. Rakesh Patel is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

#	Work	Indexed citations
1	Performance enhancement for 14nm high volume manufacturing microprocessor and system on a chip processes 2016 ·K. Fischer, (unknown), D. Ingerly, Ik Kyeong Jin, (unknown), (unknown), Rakesh Patel, C. Pelto, Cole Petersburg, P. S. Plekhanov, Conor Puls, (unknown), (unknown), (unknown), P. Yashar	9
2	The bacteriological analysis and health risks in the urban estuary of St. George's Bay, Grenada, West Indies. 2010 ·PubMed ·Rakesh Patel, (unknown), Svetlana Kotelnikova	4
3	Nonlinear behavior study in digital bang-bang PLL 2009 ·(unknown), (unknown), (unknown), (unknown), (unknown), Rakesh Patel	2
4	Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A 2007 ·(unknown), Rakesh Patel, (unknown)	3
5	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller 2007 ·(unknown), Rakesh Patel	1
6	A signal integrity-based link performance simulation platform 2006 ·(unknown), (unknown), Rakesh Patel, Sergey Shumarayev, T. Kwaśniewski	4
7	Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs 2006 ·Rakesh Patel, (unknown)	1
8	Design considerations for 2nd-order and 3rd-order bang-bang CDR loops 2006 ·(unknown), (unknown), (unknown), (unknown), T. Kwaśniewski, Rakesh Patel	6
9	Multi-protocol embedded PCS IP in a FPGA-SOC 2006 ·(unknown), (unknown), (unknown), Chong Lee, (unknown), (unknown), Tam Nguyen, (unknown), Ning Xue, (unknown), (unknown), (unknown), (unknown), (unknown), D. Vijayaraghavan, (unknown), Rakesh Patel	1
10	Managing standby and active mode leakage power in deep sub-micron design 2004 ·Lawrence T. Clark, Rakesh Patel, (unknown)	10
11	Power estimation and thermal budgeting methodology for FPGAs 2004 ·(unknown), Changhee Lee, Rakesh Patel	6
12	A user configurable gate array using CMOS-EPROM technology 2002 ·(unknown), (unknown), Rakesh Patel, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown)	1
13	Interconnect enhancements for a high-speed PLD architecture 2002 ·(unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Rakesh Patel, Bruce Pedersen, (unknown), Sergey Shumarayev	18
14	Testability features of the SuperSPARC microprocessor 2002 ·Rakesh Patel, (unknown)	8
15	A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability 2002 ·Rakesh Patel, (unknown), John Costello, (unknown), (unknown), (unknown), James D. Turner	2
16	A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 μm process 2002 ·Rakesh Patel, (unknown), (unknown), John Costello, James D. Turner	1
17	Reducing power in high-performance microprocessors 1998 ·Vivek Tiwari, (unknown), Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, (unknown)	244

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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