M. Matsuo

426 total citations
21 papers, 284 citations indexed

About

M. Matsuo is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, M. Matsuo has authored 21 papers receiving a total of 284 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 5 papers in Biomedical Engineering. Recurrent topics in M. Matsuo's work include 3D IC and TSV technologies (8 papers), Electronic Packaging and Soldering Technologies (7 papers) and Parallel Computing and Optimization Techniques (4 papers). M. Matsuo is often cited by papers focused on 3D IC and TSV technologies (8 papers), Electronic Packaging and Soldering Technologies (7 papers) and Parallel Computing and Optimization Techniques (4 papers). M. Matsuo collaborates with scholars based in Japan, United States and Germany. M. Matsuo's co-authors include N. Hayasaka, Toshihiro Itoh, Akitsu Shigetou, Tadatomo Suga, Ken-ichi Okumura, Shinji Baba, Katsuya Okumura, O.S. Nakagawa, Y. Tomita and Masahiro Yasunaga and has published in prestigious journals such as IEEE Transactions on Advanced Packaging, IEICE Transactions on Electronics and IEEE Transactions on Components Packaging and Manufacturing Technology Part A.

In The Last Decade

M. Matsuo

17 papers receiving 270 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
M. Matsuo Japan 8 270 53 41 25 25 21 284
K. Soejima Japan 8 272 1.0× 46 0.9× 33 0.8× 14 0.6× 30 1.2× 16 297
Yoichiro Kurita Japan 9 374 1.4× 67 1.3× 47 1.1× 18 0.7× 37 1.5× 32 387
Kazumasa Tanida Japan 7 344 1.3× 65 1.2× 60 1.5× 15 0.6× 32 1.3× 14 360
Riko Radojcic United States 11 282 1.0× 38 0.7× 37 0.9× 38 1.5× 13 0.5× 45 312
T. Enot France 10 241 0.9× 93 1.8× 58 1.4× 11 0.4× 11 0.4× 21 278
Xiaopeng Xu United States 10 342 1.3× 111 2.1× 25 0.6× 13 0.5× 27 1.1× 36 373
Mitsutoshi Higashi Japan 10 382 1.4× 98 1.8× 50 1.2× 44 1.8× 23 0.9× 17 389
Masaya Kawano Singapore 13 435 1.6× 80 1.5× 70 1.7× 11 0.4× 57 2.3× 45 465
Hidekazu Kikuchi Japan 8 237 0.9× 39 0.7× 61 1.5× 16 0.6× 11 0.4× 21 258
Gokul Kumar United States 6 223 0.8× 48 0.9× 22 0.5× 10 0.4× 19 0.8× 15 243

Countries citing papers authored by M. Matsuo

Since Specialization
Citations

This map shows the geographic impact of M. Matsuo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Matsuo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Matsuo more than expected).

Fields of papers citing papers by M. Matsuo

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Matsuo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Matsuo. The network helps show where M. Matsuo may publish in the future.

Co-authorship network of co-authors of M. Matsuo

This figure shows the co-authorship network connecting the top 25 collaborators of M. Matsuo. A scholar is included among the top collaborators of M. Matsuo based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Matsuo. M. Matsuo is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Azuma, Tamiko, Masahiro Sekiguchi, M. Matsuo, et al.. (2010). A novel lithography process for 3D (three-dimensional) interconnect using an optical direct-writing exposure system. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 7637. 76371O–76371O.
2.
Suzuki, Hiroaki, H. Takata, Hirofumi Shinohara, et al.. (2006). 1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit. 152–153. 1 indexed citations
3.
Ikehashi, Tamio, T. Ohguro, Hiroaki Yamazaki, et al.. (2006). A Robust RF MEMS Variable Capacitor with Piezoelectric and Electrostatic Actuation. 2. 39–42. 17 indexed citations
4.
Sekiguchi, Masahiro, et al.. (2006). Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor. 1367–1374. 27 indexed citations
5.
Shigetou, Akitsu, Toshihiro Itoh, M. Matsuo, et al.. (2006). Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method. IEEE Transactions on Advanced Packaging. 29(2). 218–226. 109 indexed citations
6.
7.
Ohguro, T., Norio Sato, M. Matsuo, et al.. (2004). Ultra-thin chip with permalloy film for high performance MS/RF CMOS. 220–221. 5 indexed citations
8.
Shimizu, Toshihisa, et al.. (2003). A 32-bit microprocessor with high performance bit-map manipulation instructions. 6. 406–409. 1 indexed citations
9.
Yasunaga, Masahiro, et al.. (2002). Chip scale package (CSP) "a lightly dressed LSI chip". 169–176. 7 indexed citations
10.
11.
Matsuo, M., et al.. (2002). Silicon interposer technology for high-density package. 1455–1459. 35 indexed citations
12.
Yoshida, Takeshi, et al.. (2002). The approach to multiple instruction execution in the GMICRO/400 processor. 185–195. 5 indexed citations
13.
14.
Baba, Shinji, et al.. (2002). Molded chip scale package for high pin count. 1251–1257. 10 indexed citations
15.
Yoshida, Takeshi, et al.. (2002). A strategy for avoiding pipeline interlock delays in a microprocessor. 12. 14–19. 1 indexed citations
16.
17.
Baba, Shinji, et al.. (1998). Molded chip scale package for high pin count. IEEE Transactions on Components Packaging and Manufacturing Technology Part B. 21(1). 28–34. 19 indexed citations
18.
Matsuo, M., et al.. (1997). An Examination of Mass Transport Paths in Conventional and Highly Textured Al-Cu Interconnect Lines. MRS Proceedings. 473. 3 indexed citations
19.
Yasunaga, Masahiro, et al.. (1995). Chip scale package: "a lightly dressed LSI chip". IEEE Transactions on Components Packaging and Manufacturing Technology Part A. 18(3). 451–457. 19 indexed citations
20.
Shimizu, Toshihisa, et al.. (1988). A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100. 30–33. 7 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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