M. Matsuo

426 citations

21 papers · 284 indexed · h-index 8

Co-authors: N. Hayasaka Toshihiro Itoh Akitsu Shigetou Tadatomo Suga Ken-ichi Okumura Shinji Baba Katsuya Okumura Y. Tomita
Topics: 3D IC and TSV technologies (8 papers)Electronic Packaging and Soldering Technologies (7 papers)Parallel Computing and Optimization Techniques (4 papers)
Cited by: Electrical and Electronic Engineering Hardware and Architecture Automotive Engineering
Journals: IEEE Transactions on Advanced Packaging IEEE Transactions on Components Packaging and Manufacturing Technology Part A IEICE Transactions on Electronics
Partner nations: Japan United States Germany

In The Last Decade

M. Matsuo

17 papers receiving 270 citations

Peers

Countries citing papers authored by M. Matsuo

Since Specialization

Citations

This map shows the geographic impact of M. Matsuo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Matsuo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Matsuo more than expected).

Fields of papers citing papers by M. Matsuo

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Matsuo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Matsuo. The network helps show where M. Matsuo may publish in the future.

Co-authorship network of co-authors of M. Matsuo

This figure shows the co-authorship network connecting the top 25 collaborators of M. Matsuo. A scholar is included among the top collaborators of M. Matsuo based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Matsuo. M. Matsuo is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	A novel lithography process for 3D (three-dimensional) interconnect using an optical direct-writing exposure system 2010 ·Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tamiko Azuma,Masahiro Sekiguchi,M. Matsuo,(unknown),K. Hagiwara,(unknown),Naoko Kawamura,(unknown),Atsushi Nakamura,(unknown)	0
2	1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit 2006 ·Hiroaki Suzuki,H. Takata,Hirofumi Shinohara,(unknown),M. Matsuo,Takeshi Yoshida,H. Sato,(unknown),(unknown),Toshihisa Shimizu	1
3	A Robust RF MEMS Variable Capacitor with Piezoelectric and Electrostatic Actuation 2006 ·Tamio Ikehashi,T. Ohguro,(unknown),Hiroaki Yamazaki,Kazunobu Kojima,M. Matsuo,K. Ishimaru,H. Ishiuchi	17
4	Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor 2006 ·Masahiro Sekiguchi,(unknown),Naoki Sato,(unknown),M. Matsuo,Hiroshi Yoshikawa,(unknown),(unknown),Kenji Takahashi	27
5	Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method 2006 ·IEEE Transactions on Advanced Packaging ·Akitsu Shigetou,Toshihiro Itoh,M. Matsuo,N. Hayasaka,Ken-ichi Okumura,Tadatomo Suga	109
6	Room temperature bonding of ultra-fine pitch and low-profiled Cu electrodes for bump-less interconnect 2004 ·Akitsu Shigetou,Toshihiro Itoh,M. Matsuo,N. Hayasaka,(unknown),Tadatomo Suga	6
7	Ultra-thin chip with permalloy film for high performance MS/RF CMOS 2004 ·T. Ohguro,Norio Sato,M. Matsuo,Kazunobu Kojima,H.S. Momose,K. Ishimaru,H. Ishiuchi	5
8	A 32-bit microprocessor with high performance bit-map manipulation instructions 2003 ·Toshihisa Shimizu,(unknown),(unknown),Takeshi Yoshida,M. Matsuo,(unknown),(unknown)	1
9	A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface 2002 ·M. Matsuo,Hiroyuki Kondo,(unknown),(unknown),(unknown),Takeshi Yoshida,(unknown),(unknown)	0
10	Chip scale package (CSP) "a lightly dressed LSI chip" 2002 ·Masahiro Yasunaga,Shinji Baba,M. Matsuo,(unknown),S. Nakao,(unknown)	7
11	Silicon interposer technology for high-density package 2002 ·M. Matsuo,N. Hayasaka,Katsuya Okumura,(unknown),(unknown)	35
12	The approach to multiple instruction execution in the GMICRO/400 processor 2002 ·Takeshi Yoshida,M. Matsuo,(unknown)	5
13	Molded chip scale package for high pin count 2002 ·Shinji Baba,Y. Tomita,M. Matsuo,(unknown),(unknown),O.S. Nakagawa	10
14	A strategy for avoiding pipeline interlock delays in a microprocessor 2002 ·Takeshi Yoshida,M. Matsuo,Tetsuya Ueda,(unknown)	1
15	The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory 2002 ·(unknown),(unknown),(unknown),Hajime Shirai,M. Matsuo,(unknown),(unknown),S. Saito,K.I. Arai,(unknown)	11
16	A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems 2002 ·(unknown),Tetsuya Ueda,M. Matsuo,(unknown),(unknown),(unknown),Takeshi Yoshida,(unknown),(unknown)	0
17	Molded chip scale package for high pin count 1998 ·IEEE Transactions on Components Packaging and Manufacturing Technology Part B ·Shinji Baba,Y. Tomita,M. Matsuo,(unknown),(unknown),O.S. Nakagawa	19
18	An Examination of Mass Transport Paths in Conventional and Highly Textured Al-Cu Interconnect Lines 1997 ·MRS Proceedings ·(unknown),(unknown),M. Matsuo,Hiroshi Toyoda,William D. Nix	3
19	Chip scale package: "a lightly dressed LSI chip" 1995 ·IEEE Transactions on Components Packaging and Manufacturing Technology Part A ·Masahiro Yasunaga,Shinji Baba,M. Matsuo,(unknown),S. Nakao,(unknown)	19
20	A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100 1988 ·Toshihisa Shimizu,Takeshi Yoshida,(unknown),M. Matsuo,(unknown)	7

About M. Matsuo

M. Matsuo is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Electronic, Optical and Magnetic Materials, having authored 21 papers that have together received 284 indexed citations. Recurring topics across this work include 3D IC and TSV technologies (8 papers), Electronic Packaging and Soldering Technologies (7 papers) and Parallel Computing and Optimization Techniques (4 papers). The work is most often cited by research in Electrical and Electronic Engineering (270 citations), Hardware and Architecture (25 citations) and Automotive Engineering (41 citations). M. Matsuo has collaborated with scholars based in Japan, United States and Germany. Frequent co-authors include N. Hayasaka, Toshihiro Itoh, Akitsu Shigetou, Tadatomo Suga, Ken-ichi Okumura, Shinji Baba, Katsuya Okumura, Y. Tomita, O.S. Nakagawa and Takeshi Yoshida. Their work appears in journals such as IEEE Transactions on Advanced Packaging, IEEE Transactions on Components Packaging and Manufacturing Technology Part A and IEICE Transactions on Electronics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact