Kuo‐Hsing Cheng

1.5k total citations
102 papers, 910 citations indexed

About

Kuo‐Hsing Cheng is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Kuo‐Hsing Cheng has authored 102 papers receiving a total of 910 indexed citations (citations by other indexed papers that have themselves been cited), including 93 papers in Electrical and Electronic Engineering, 63 papers in Biomedical Engineering and 18 papers in Hardware and Architecture. Recurrent topics in Kuo‐Hsing Cheng's work include Advancements in PLL and VCO Technologies (66 papers), Analog and Mixed-Signal Circuit Design (62 papers) and Radio Frequency Integrated Circuit Design (30 papers). Kuo‐Hsing Cheng is often cited by papers focused on Advancements in PLL and VCO Technologies (66 papers), Analog and Mixed-Signal Circuit Design (62 papers) and Radio Frequency Integrated Circuit Design (30 papers). Kuo‐Hsing Cheng collaborates with scholars based in Taiwan and United States. Kuo‐Hsing Cheng's co-authors include Yu-Lung Lo, Wei-Bin Yang, Jen‐Chieh Liu, Hong‐Yi Huang, Chih-Sheng Huang, Chung‐Yu Wu, Masayoshi Tomizuka, Heng-Yuan Lee, Pang-Shiu Chen and Wen-Pin Lin and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IEEE Transactions on Fuzzy Systems.

In The Last Decade

Kuo‐Hsing Cheng

91 papers receiving 860 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Kuo‐Hsing Cheng Taiwan 17 798 394 116 57 49 102 910
Daeyeon Kim United States 16 905 1.1× 221 0.6× 156 1.3× 112 2.0× 39 0.8× 54 1.1k
Pierangelo Terreni Italy 11 549 0.7× 361 0.9× 78 0.7× 76 1.3× 24 0.5× 68 681
J.E. Franca Portugal 14 695 0.9× 614 1.6× 96 0.8× 99 1.7× 28 0.6× 140 821
Ayman Fayed United States 19 891 1.1× 343 0.9× 67 0.6× 30 0.5× 45 0.9× 68 929
João Goês Portugal 16 838 1.1× 600 1.5× 74 0.6× 64 1.1× 27 0.6× 141 946
Emre Salman United States 15 689 0.9× 173 0.4× 229 2.0× 78 1.4× 6 0.1× 99 852
Matthias Brändli Switzerland 15 967 1.2× 399 1.0× 61 0.5× 46 0.8× 28 0.6× 41 994
Xu Cheng China 13 719 0.9× 119 0.3× 98 0.8× 44 0.8× 59 1.2× 79 875
Mohammad Maymandi‐Nejad Iran 15 624 0.8× 453 1.1× 73 0.6× 48 0.8× 5 0.1× 64 747

Countries citing papers authored by Kuo‐Hsing Cheng

Since Specialization
Citations

This map shows the geographic impact of Kuo‐Hsing Cheng's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kuo‐Hsing Cheng with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kuo‐Hsing Cheng more than expected).

Fields of papers citing papers by Kuo‐Hsing Cheng

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kuo‐Hsing Cheng. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kuo‐Hsing Cheng. The network helps show where Kuo‐Hsing Cheng may publish in the future.

Co-authorship network of co-authors of Kuo‐Hsing Cheng

This figure shows the co-authorship network connecting the top 25 collaborators of Kuo‐Hsing Cheng. A scholar is included among the top collaborators of Kuo‐Hsing Cheng based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kuo‐Hsing Cheng. Kuo‐Hsing Cheng is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Cheng, Kuo‐Hsing, et al.. (2024). A 10 Gb/s Full-Rate Receiver with RX-FFE Compensation. 1–4.
2.
Cheng, Kuo‐Hsing, et al.. (2021). A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(10). 1720–1729. 6 indexed citations
3.
Tsai, Pei‐Yun, et al.. (2017). A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. 101. 1–4. 3 indexed citations
4.
Huang, Yuanhui, et al.. (2014). Microdosimetry spectra and relative biological effectiveness of 15 and 30 MeV proton beams. Applied Radiation and Isotopes. 97. 101–105. 14 indexed citations
5.
Cheng, Kuo‐Hsing, et al.. (2013). A wide supply voltage range and low-power all-digital clock generator. Analog Integrated Circuits and Signal Processing. 74(3). 517–526. 1 indexed citations
6.
Chang, Chi-Yang, et al.. (2011). A 3 GHz spread-spectrum clock generator with a self-calibration technique. 177–180. 2 indexed citations
7.
Cheng, Kuo‐Hsing, et al.. (2010). A CMOS adaptive equalizer using low-voltage zero generators technique. 41. 546–549. 2 indexed citations
8.
Cheng, Kuo‐Hsing, et al.. (2009). A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17(12). 1698–1708. 10 indexed citations
9.
Lo, Yu-Lung, et al.. (2009). High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Transactions on Electronics. E92-C(6). 890–893. 1 indexed citations
10.
11.
Cheng, Kuo‐Hsing, et al.. (2007). A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. 363–366. 3 indexed citations
12.
Huang, Hongyi, Jen‐Chieh Liu, & Kuo‐Hsing Cheng. (2007). All-Digital PLL Using Pulse-Based DCO. 1268–1271. 6 indexed citations
13.
Cheng, Kuo‐Hsing & Yu-Lung Lo. (2007). A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing. 54(7). 561–565. 34 indexed citations
14.
Cheng, Kuo‐Hsing & Yu-Lung Lo. (2005). A fast-lock mixed-mode dll with wide-range operation and multiphase outputs. 189–192. 4 indexed citations
15.
Cheng, Kuo‐Hsing, et al.. (2004). A CMOS VCO for 1V, 1GHz PLL applications. 150–153. 10 indexed citations
16.
Cheng, Kuo‐Hsing & Chih-Sheng Huang. (2003). The novel efficient design of XOR/XNOR function for adder applications. 1. 29–32. 20 indexed citations
17.
Cheng, Kuo‐Hsing, et al.. (2003). BIST for clock jitter measurements. 5. V–577. 4 indexed citations
18.
Cheng, Kuo‐Hsing, et al.. (2002). Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. Asia and South Pacific Design Automation Conference. 155–159.
19.
20.
Wu, Chung‐Yu, et al.. (1993). Analysis and design of a new race-free four-phase CMOS logic. IEEE Journal of Solid-State Circuits. 28(1). 18–25. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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2026