José T. de Sousa

770 total citations
49 papers, 487 citations indexed

About

José T. de Sousa is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Vision and Pattern Recognition. According to data from OpenAlex, José T. de Sousa has authored 49 papers receiving a total of 487 indexed citations (citations by other indexed papers that have themselves been cited), including 34 papers in Electrical and Electronic Engineering, 27 papers in Hardware and Architecture and 10 papers in Computer Vision and Pattern Recognition. Recurrent topics in José T. de Sousa's work include VLSI and Analog Circuit Testing (20 papers), Integrated Circuits and Semiconductor Failure Analysis (14 papers) and Advanced Neural Network Applications (10 papers). José T. de Sousa is often cited by papers focused on VLSI and Analog Circuit Testing (20 papers), Integrated Circuits and Semiconductor Failure Analysis (14 papers) and Advanced Neural Network Applications (10 papers). José T. de Sousa collaborates with scholars based in Portugal, United Kingdom and United States. José T. de Sousa's co-authors include Mário Véstias, Horácio C. Neto, Rui Policarpo Duarte, M. Abramovici, F.M. Gonçalves, J.P. Teixeira, Vishwani D. Agrawal, T.W. Williams, D.G. Saab and C. Marzocca and has published in prestigious journals such as IEEE Access, IEEE Journal of Solid-State Circuits and IEEE Transactions on Microwave Theory and Techniques.

In The Last Decade

José T. de Sousa

46 papers receiving 465 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
José T. de Sousa Portugal	13	290	192	138	79	79	49	487
Hiroyuki Ochi Japan	11	334 1.2×	206 1.1×	122 0.9×	65 0.8×	22 0.3×	71	490
Giulio Gambardella Italy	12	301 1.0×	171 0.9×	233 1.7×	77 1.0×	152 1.9×	28	537
Peichen Pan United States	12	597 2.1×	423 2.2×	287 2.1×	145 1.8×	147 1.9×	26	849
Maksim Jenihhin Estonia	12	328 1.1×	248 1.3×	24 0.2×	63 0.8×	70 0.9×	109	498
Ali Mahani Iran	11	231 0.8×	86 0.4×	38 0.3×	159 2.0×	129 1.6×	69	428
Daniel Ménard France	15	207 0.7×	143 0.7×	362 2.6×	79 1.0×	39 0.5×	76	727
Doran Wilde United States	10	51 0.2×	252 1.3×	81 0.6×	155 2.0×	91 1.2×	33	460
Mariusz Rawski Poland	11	176 0.6×	212 1.1×	32 0.2×	76 1.0×	86 1.1×	68	412
R. Stefanelli Italy	11	312 1.1×	279 1.5×	224 1.6×	247 3.1×	95 1.2×	62	706
Ken Choi United States	14	530 1.8×	181 0.9×	95 0.7×	69 0.9×	56 0.7×	80	724

Countries citing papers authored by José T. de Sousa

Since Specialization

Citations

This map shows the geographic impact of José T. de Sousa's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by José T. de Sousa with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites José T. de Sousa more than expected).

Fields of papers citing papers by José T. de Sousa

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by José T. de Sousa. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by José T. de Sousa. The network helps show where José T. de Sousa may publish in the future.

Co-authorship network of co-authors of José T. de Sousa

This figure shows the co-authorship network connecting the top 25 collaborators of José T. de Sousa. A scholar is included among the top collaborators of José T. de Sousa based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with José T. de Sousa. José T. de Sousa is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

1.

Sousa, José T. de, et al.. (2024). PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. 139–146. 1 indexed citations

2.

Mota, David F., et al.. (2022). Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing. 15. 3600–3611. 11 indexed citations

3.

Véstias, Mário, et al.. (2021). IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms. 14(8). 218–218. 3 indexed citations

4.

Véstias, Mário, Rui Policarpo Duarte, José T. de Sousa, & Horácio C. Neto. (2020). Moving Deep Learning to the Edge. Algorithms. 13(5). 125–125. 47 indexed citations

5.

Gonçalves, F.M., et al.. (2019). Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. 6 indexed citations

6.

Sousa, José T. de, et al.. (2018). A 1.7-mW −92-dBm Sensitivity Low-IF Receiver in 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS for Bluetooth LE Applications. IEEE Transactions on Microwave Theory and Techniques. 67(1). 332–346. 30 indexed citations

7.

Véstias, Mário, Rui Policarpo Duarte, José T. de Sousa, & Horácio C. Neto. (2017). Parallel dot-products for deep learning on FPGA. 1–4. 24 indexed citations

8.

Sousa, José T. de, et al.. (2006). A Fast SAT Solver Strategy Based on Negated Clauses. c 28. 110–115. 2 indexed citations

9.

Sousa, José T. de, et al.. (2006). A fast SAT solver algorithm best suited to reconfigurable hardware. 22. 131–136. 1 indexed citations

10.

Sousa, José T. de, et al.. (2005). A low-cost scalable pipelined reconfigurable architecture for simulation of digital circuits. 481–486.

11.

Sousa, José T. de, F.M. Gonçalves, & J.P. Teixeira. (2005). IC DEFECTS-BASED TESTABILITY ANALYSIS. 500–500. 5 indexed citations

12.

Abramovici, M. & José T. de Sousa. (2003). A virtual logic algorithm for solving satisfiability problems using reconfigurable hardware. 306–307. 3 indexed citations

13.

Sousa, José T. de, F.M. Gonçalves, J.P. Teixeira, & T.W. Williams. (2002). Fault modeling and defect level projections in digital ICs. 436–442. 10 indexed citations

14.

Braceras, G., et al.. (2002). A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 μm CMOS process. 404–405,. 4 indexed citations

15.

Sousa, José T. de, et al.. (2001). A Configurable Hardware/Software Approach to SAT Solving. 239–248. 10 indexed citations

16.

Sousa, José T. de & Peter Y. K. Cheung. (1997). Improved diagnosis of realistic interconnect shorts. 501–505. 1 indexed citations

17.

Sousa, José T. de, et al.. (1996). Realistic fault extraction for boards. 612. 3 indexed citations

18.

Sousa, José T. de, et al.. (1996). A 2 ns zero wait state, 32 kB semi-associative L1 cache. 154–155. 6 indexed citations

19.

Sousa, José T. de, F.M. Gonçalves, & J.P. Teixeira. (1991). High-quality physical designs of CMOS ICs. 310–315. 2 indexed citations

20.

Teixeira, J.P., F.M. Gonçalves, & José T. de Sousa. (1990). On the Physical Design of Testable CMOS Digital Circuits. European Solid-State Circuits Conference. 1. 109–112.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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