Peichen Pan

1.3k total citations
26 papers, 849 citations indexed

About

Peichen Pan is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, Peichen Pan has authored 26 papers receiving a total of 849 indexed citations (citations by other indexed papers that have themselves been cited), including 23 papers in Electrical and Electronic Engineering, 18 papers in Hardware and Architecture and 5 papers in Computational Theory and Mathematics. Recurrent topics in Peichen Pan's work include VLSI and FPGA Design Techniques (20 papers), VLSI and Analog Circuit Testing (14 papers) and Low-power high-performance VLSI design (10 papers). Peichen Pan is often cited by papers focused on VLSI and FPGA Design Techniques (20 papers), VLSI and Analog Circuit Testing (14 papers) and Low-power high-performance VLSI design (10 papers). Peichen Pan collaborates with scholars based in United States, Taiwan and China. Peichen Pan's co-authors include Jason Cong, Chen Zhang, Peipei Zhou, Zhenman Fang, Chih-Chang Lin, Guangyu Sun, Deming Chen, Jason Cong, C.L. Liu and C.L. Liu and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Algorithmica and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Peichen Pan

24 papers receiving 806 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Peichen Pan United States	12	597	423	287	147	145	26	849
R. Stefanelli Italy	11	312 0.5×	279 0.7×	224 0.8×	95 0.6×	247 1.7×	62	706
P.M. Chau United States	13	299 0.5×	243 0.6×	250 0.9×	116 0.8×	141 1.0×	84	740
Bart Mesman Netherlands	14	275 0.5×	469 1.1×	271 0.9×	114 0.8×	328 2.3×	56	763
Xuegong Zhou China	11	305 0.5×	189 0.4×	253 0.9×	119 0.8×	99 0.7×	42	537
José T. de Sousa Portugal	13	290 0.5×	192 0.5×	138 0.5×	79 0.5×	79 0.5×	49	487
Brian Richards United States	12	470 0.8×	656 1.6×	88 0.3×	141 1.0×	328 2.3×	35	1.1k
Ritchie Zhao United States	12	297 0.5×	317 0.7×	263 0.9×	180 1.2×	181 1.2×	15	660
Naveen Suda United States	10	624 1.0×	191 0.5×	686 2.4×	411 2.8×	120 0.8×	15	1.1k
Robert Adolf United States	7	427 0.7×	347 0.8×	295 1.0×	227 1.5×	190 1.3×	11	783
Divya Mahajan United States	13	536 0.9×	380 0.9×	266 0.9×	213 1.4×	205 1.4×	31	873

Countries citing papers authored by Peichen Pan

Since Specialization

Citations

This map shows the geographic impact of Peichen Pan's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Peichen Pan with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Peichen Pan more than expected).

Fields of papers citing papers by Peichen Pan

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Peichen Pan. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Peichen Pan. The network helps show where Peichen Pan may publish in the future.

Co-authorship network of co-authors of Peichen Pan

This figure shows the co-authorship network connecting the top 25 collaborators of Peichen Pan. A scholar is included among the top collaborators of Peichen Pan based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Peichen Pan. Peichen Pan is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Pan, Peichen, et al.. (2025). Fast Synchronization and Cell Identification via the Overlapped Fast Fourier Transform for the 5G New Radio and V2X Communications. IEICE Transactions on Communications. E108-B(7). 811–818.

Cong, Jason, Jason Lau, Gai Liu, et al.. (2022). FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Transactions on Reconfigurable Technology and Systems. 15(4). 1–42. 85 indexed citations

Zhang, Chen, Guangyu Sun, Zhenman Fang, et al.. (2018). Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38(11). 2072–2085. 189 indexed citations

Zhang, Chen, Zhenman Fang, Peipei Zhou, Peichen Pan, & Jason Cong. (2016). Caffeine. 1–8. 211 indexed citations

Cong, Jason, et al.. (2016). Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers. 154–155. 15 indexed citations

Chen, Deming, Jason Cong, & Peichen Pan. (2006). FPGA Design Automation: A Survey. 1(3). 195–330. 66 indexed citations

Pan, Peichen, et al.. (2005). Optimal clock period FPGA technology mapping for sequential circuits. 720–725. 1 indexed citations

Dasgupta, Parthasarathi, Peichen Pan, Subhas C. Nandy, & Bhargab B. Bhattacharya. (2002). Monotone bipartitioning problem in a planar point set with applications to VLSI. ACM Transactions on Design Automation of Electronic Systems. 7(2). 231–248. 6 indexed citations

Pan, Peichen. (1999). Performance-driven integration of retiming and resynthesis. 243–246. 7 indexed citations

10.

Pan, Peichen, et al.. (1999). Optimal retiming for initial state computation. 366–371. 3 indexed citations

11.

Pan, Peichen & Chih-Chang Lin. (1998). A new retiming-based technology mapping algorithm for LUT-based FPGAs. 35–42. 75 indexed citations

12.

Pan, Peichen, et al.. (1998). Low power logic synthesis under a general delay model. 209–214. 10 indexed citations

13.

Pan, Peichen, et al.. (1998). Optimal clock period clustering for sequential circuits with retiming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17(6). 489–498. 48 indexed citations

14.

Pan, Peichen & C.L. Liu. (1996). Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. 58–64. 1 indexed citations

15.

Pan, Peichen & C.L. Liu. (1996). Technology mapping of sequential circuits for LUT-based FPGAs for performance. 58–64. 12 indexed citations

16.

Pan, Peichen, Weiping Shi, & C. L. Liu. (1996). Area minimization for hierarchical floorplans. Algorithmica. 15(6). 550–571. 8 indexed citations

17.

Pan, Peichen & C.L. Liu. (1995). Area minimization for floorplans. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14(1). 123–132. 35 indexed citations

18.

Pan, Peichen, Weiping Shi, & C.L. Liu. (1994). Area minimization for hierarchical floorplans. International Conference on Computer Aided Design. 436–440. 7 indexed citations

19.

Pan, Peichen, et al.. (1993). Optimal graph constraint reduction for symbolic layout compaction. 401–406. 6 indexed citations

20.

Pan, Peichen & C. L. Liu. (1992). Area minimization for general floorplans. International Conference on Computer Aided Design. 1992. 606–609. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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