D. Overhauser

436 total citations
20 papers, 304 citations indexed

About

D. Overhauser is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, D. Overhauser has authored 20 papers receiving a total of 304 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Electrical and Electronic Engineering, 12 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in D. Overhauser's work include Low-power high-performance VLSI design (18 papers), VLSI and Analog Circuit Testing (11 papers) and VLSI and FPGA Design Techniques (7 papers). D. Overhauser is often cited by papers focused on Low-power high-performance VLSI design (18 papers), VLSI and Analog Circuit Testing (11 papers) and VLSI and FPGA Design Techniques (7 papers). D. Overhauser collaborates with scholars based in United States and South Korea. D. Overhauser's co-authors include R. Saleh, Syed Zeeshan Hussain, Jeong-Taek Kong, J. R. Lloyd, M Benoit, Izzat El Hajj, Yi Wang, Yucheng Wang and Yu-Pin Hsu and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Microelectronics Reliability and IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications.

In The Last Decade

D. Overhauser

20 papers receiving 281 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
D. Overhauser United States 10 289 119 39 28 9 20 304
Chanhee Oh United States 10 471 1.6× 257 2.2× 28 0.7× 27 1.0× 20 2.2× 23 478
K.N. Quader United States 10 369 1.3× 47 0.4× 22 0.6× 20 0.7× 8 0.9× 20 403
W.H. Kao United States 9 258 0.9× 171 1.4× 8 0.2× 22 0.8× 16 1.8× 24 295
T. Noguchi Japan 9 233 0.8× 47 0.4× 11 0.3× 46 1.6× 25 2.8× 26 247
E. Hamdy United States 10 286 1.0× 101 0.8× 7 0.2× 28 1.0× 5 0.6× 34 305
Bogdan Tutuianu United States 5 447 1.5× 221 1.9× 5 0.1× 32 1.1× 14 1.6× 6 461
Yujeong Shim South Korea 12 328 1.1× 16 0.1× 30 0.8× 17 0.6× 3 0.3× 43 337
Behzad Ebrahimi Iran 12 401 1.4× 50 0.4× 8 0.2× 32 1.1× 16 1.8× 45 412
T. G. McNamara United States 8 409 1.4× 181 1.5× 10 0.3× 34 1.2× 4 0.4× 12 421
S. Minehane Ireland 9 370 1.3× 82 0.7× 5 0.1× 36 1.3× 25 2.8× 18 390

Countries citing papers authored by D. Overhauser

Since Specialization
Citations

This map shows the geographic impact of D. Overhauser's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Overhauser with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Overhauser more than expected).

Fields of papers citing papers by D. Overhauser

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Overhauser. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Overhauser. The network helps show where D. Overhauser may publish in the future.

Co-authorship network of co-authors of D. Overhauser

This figure shows the co-authorship network connecting the top 25 collaborators of D. Overhauser. A scholar is included among the top collaborators of D. Overhauser based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Overhauser. D. Overhauser is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Overhauser, D. & Izzat El Hajj. (2003). A tabular macromodeling approach to fast timing simulation including parasitics. 70–73. 1 indexed citations
2.
Hussain, Syed Zeeshan, et al.. (2003). Clock verification in the presence of IR-drop in the power distribution network. 437–440. 4 indexed citations
3.
Overhauser, D. & Izzat El Hajj. (2003). Multi-level circuit partitioning for switch-level timing simulation. cad 1. 1361–1364. 1 indexed citations
4.
Overhauser, D., Izzat El Hajj, & Yu-Pin Hsu. (2003). Automatic mixed-mode timing simulation. 84–87. 1 indexed citations
5.
Overhauser, D., et al.. (2002). Combining RC-interconnect effects with nonlinear MOS macromodels. 1. 570–573. 2 indexed citations
6.
Wang, Yucheng, et al.. (2002). Accurate parasitic resistance extraction for interconnection analysis. 255–258. 3 indexed citations
7.
Overhauser, D. & R. Saleh. (2002). Evaluating mixed-signal simulators. 113–120. 3 indexed citations
8.
Overhauser, D. & Izzat El Hajj. (2002). IDSIM2: an environment for mixed-mode simulation. cad 8. 5.2/1–5.2/4. 1 indexed citations
9.
Saleh, R., et al.. (2002). Benchmark circuits for mixed-mode simulators. 28. 441–448. 3 indexed citations
10.
Overhauser, D., et al.. (2002). A novel graph algorithm for circuit recognition. 3. 1695–1698. 9 indexed citations
11.
Saleh, R., et al.. (2000). Clock skew verification in the presence of IR-drop in the power distribution network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19(6). 635–644. 78 indexed citations
12.
Saleh, R., et al.. (1998). Full-chip verification of UDSM designs. 453–460. 13 indexed citations
13.
Overhauser, D., et al.. (1998). Full-chip reliability analysis. Microelectronics Reliability. 38(6-8). 851–859. 15 indexed citations
14.
Overhauser, D., et al.. (1998). Full-chip verification methods for DSM power distribution systems. 744–749. 74 indexed citations
15.
Lloyd, J. R., et al.. (1998). Full-chip reliability analysis. 356–362. 22 indexed citations
16.
Benoit, M, et al.. (1998). Power distribution in high-performance design. 274–278. 16 indexed citations
17.
Overhauser, D., et al.. (1997). Performance estimation of complex MOS gates. IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications. 44(9). 785–795. 14 indexed citations
18.
Kong, Jeong-Taek & D. Overhauser. (1995). Methods to improve digital MOS macromodel accuracy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14(7). 868–881. 23 indexed citations
19.
Kong, Jeong-Taek & D. Overhauser. (1995). Digital Timing Macromodeling for VLSI Design Verification. 10 indexed citations
20.
Overhauser, D.. (1989). Fast timing simulation of mos vlsi circuits. IDEALS (University of Illinois Urbana-Champaign). 11 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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