Edward Stott

488 total citations
19 papers, 362 citations indexed

About

Edward Stott is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Edward Stott has authored 19 papers receiving a total of 362 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in Edward Stott's work include Low-power high-performance VLSI design (10 papers), Parallel Computing and Optimization Techniques (7 papers) and VLSI and Analog Circuit Testing (6 papers). Edward Stott is often cited by papers focused on Low-power high-performance VLSI design (10 papers), Parallel Computing and Optimization Techniques (7 papers) and VLSI and Analog Circuit Testing (6 papers). Edward Stott collaborates with scholars based in United Kingdom and Singapore. Edward Stott's co-authors include Peter Y. K. Cheung, Pete Sedcole, Justin S. J. Wong, Joshua M. Levine, George A. Constantinides, James J. Davis, Geoff V. Merrett, Bashir M. Al‐Hashimi, Rishad Shafik and Sheng Yang and has published in prestigious journals such as IEEE Design and Test, ACM Transactions on Reconfigurable Technology and Systems and Spiral (Imperial College London).

In The Last Decade

Edward Stott

18 papers receiving 348 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Edward Stott United Kingdom	10	312	253	66	21	16	19	362
Andy Ye Canada	8	287 0.9×	241 1.0×	64 1.0×	12 0.6×	14 0.9×	36	342
Mohsen Raji Iran	10	254 0.8×	135 0.5×	33 0.5×	25 1.2×	20 1.3×	49	295
Shih‐Lien L. Lu United States	10	587 1.9×	373 1.5×	109 1.7×	33 1.6×	55 3.4×	19	675
Gabriel L. Nazar Brazil	10	252 0.8×	203 0.8×	88 1.3×	25 1.2×	5 0.3×	58	307
Themistoklis Haniotakis United States	11	285 0.9×	140 0.6×	81 1.2×	19 0.9×	49 3.1×	59	362
Claudio Mucci Italy	9	102 0.3×	228 0.9×	188 2.8×	23 1.1×	9 0.6×	33	279
Sean White United States	6	166 0.5×	193 0.8×	179 2.7×	24 1.1×	7 0.4×	13	321
David M. Bull United Kingdom	8	525 1.7×	275 1.1×	60 0.9×	22 1.0×	77 4.8×	12	577
Paul S. Zuchowski United States	7	402 1.3×	319 1.3×	123 1.9×	9 0.4×	31 1.9×	11	479
David Greenhill United States	5	160 0.5×	161 0.6×	129 2.0×	13 0.6×	10 0.6×	8	252

Countries citing papers authored by Edward Stott

Since Specialization

Citations

This map shows the geographic impact of Edward Stott's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Edward Stott with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Edward Stott more than expected).

Fields of papers citing papers by Edward Stott

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Edward Stott. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Edward Stott. The network helps show where Edward Stott may publish in the future.

Co-authorship network of co-authors of Edward Stott

This figure shows the co-authorship network connecting the top 25 collaborators of Edward Stott. A scholar is included among the top collaborators of Edward Stott based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Edward Stott. Edward Stott is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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19 of 19 papers shown

Davis, James J., Eddie Hung, Joshua M. Levine, et al.. (2018). KAPow. ACM Transactions on Reconfigurable Technology and Systems. 11(1). 1–22. 9 indexed citations

Davis, James J., Joshua M. Levine, Edward Stott, et al.. (2017). STRIPE: Signal selection for runtime power estimation. Spiral (Imperial College London). 1–8. 4 indexed citations

Davis, James J., Joshua M. Levine, Edward Stott, et al.. (2017). KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Design and Test. 34(6). 36–45. 1 indexed citations

Hung, Eddie, James J. Davis, Joshua M. Levine, et al.. (2016). KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. Spiral (Imperial College London). 48. 56–63. 9 indexed citations

Yang, Sheng, Rishad Shafik, Geoff V. Merrett, et al.. (2015). Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. ePrints Soton (University of Southampton). 103–110. 35 indexed citations

Hung, Eddie, Joshua M. Levine, Edward Stott, George A. Constantinides, & Wayne Luk. (2015). Delay-Bounded Routing for Shadow Registers. 56–65. 1 indexed citations

Boland, David, et al.. (2014). Datapath Synthesis for Overclocking. 1–6. 13 indexed citations

Stott, Edward, Joshua M. Levine, Peter Y. K. Cheung, & Nachiket Kapre. (2014). Timing Fault Detection in FPGA-Based Circuits. DR-NTU (Nanyang Technological University). 96–99. 8 indexed citations

Levine, Joshua M., Edward Stott, & Peter Y. K. Cheung. (2014). Dynamic voltage & frequency scaling with online slack measurement. 65–74. 32 indexed citations

10.

Stott, Edward, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, & Peter Y. K. Cheung. (2013). Variation and Reliability in FPGAs. IEEE Design and Test. 30(6). 50–59. 8 indexed citations

11.

Levine, Joshua M., Edward Stott, George A. Constantinides, & Peter Y. K. Cheung. (2013). SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. 1–4. 10 indexed citations

12.

Levine, Joshua M., Edward Stott, George A. Constantinides, & Peter Y. K. Cheung. (2012). Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. 109–116. 24 indexed citations

13.

Levine, Joshua M., Edward Stott, George A. Constantinides, & Peter Y. K. Cheung. (2011). Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). 284–284. 1 indexed citations

14.

Stott, Edward & Peter Y. K. Cheung. (2011). Improving FPGA Reliability with Wear-Levelling. 323–328. 21 indexed citations

15.

Stott, Edward, Justin S. J. Wong, Pete Sedcole, & Peter Y. K. Cheung. (2010). Degradation in FPGAs. 229–238. 80 indexed citations

16.

Stott, Edward, Justin S. J. Wong, & Peter Y. K. Cheung. (2010). Degradation Analysis and Mitigation in FPGAs. 428–433. 47 indexed citations

17.

Stott, Edward, Pete Sedcole, & Peter Y. K. Cheung. (2009). Modelling degradation in FPGA lookup tables. 32. 443–446. 8 indexed citations

18.

Sedcole, Pete, Edward Stott, & Peter Y. K. Cheung. (2009). Compensating for variability in FPGAs by re-mapping and re-placement. 613–616. 6 indexed citations

19.

Stott, Edward, Pete Sedcole, & Peter Y. K. Cheung. (2008). Fault tolerant methods for reliability in FPGAs. 415–420. 45 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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