C. L. Liu

1.1k total citations
21 papers, 800 citations indexed

About

C. L. Liu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, C. L. Liu has authored 21 papers receiving a total of 800 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 12 papers in Hardware and Architecture and 5 papers in Computer Networks and Communications. Recurrent topics in C. L. Liu's work include VLSI and FPGA Design Techniques (14 papers), VLSI and Analog Circuit Testing (8 papers) and Low-power high-performance VLSI design (6 papers). C. L. Liu is often cited by papers focused on VLSI and FPGA Design Techniques (14 papers), VLSI and Analog Circuit Testing (8 papers) and Low-power high-performance VLSI design (6 papers). C. L. Liu collaborates with scholars based in United States, Singapore and Switzerland. C. L. Liu's co-authors include Martin D. F. Wong, Wai Yie Leong, Ran Libeskind-Hadas, Peichen Pan, Jason Cong, Bryan Preas, Ki‐Seok Chung, C. K. Wong, Weiping Shi and Chris K.C. Wong and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Algorithmica and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

C. L. Liu

21 papers receiving 752 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
C. L. Liu United States	11	654	391	191	148	80	21	800
Ralph H. J. M. Otten Netherlands	12	589 0.9×	344 0.9×	168 0.9×	103 0.7×	60 0.8×	24	706
Jiří Soukup Canada	9	402 0.6×	247 0.6×	135 0.7×	41 0.3×	55 0.7×	24	526
Andrew Kennings Canada	17	527 0.8×	455 1.2×	106 0.6×	147 1.0×	64 0.8×	60	765
A.E. Dunlop United States	12	928 1.4×	600 1.5×	157 0.8×	51 0.3×	74 0.9×	17	1.0k
M. Hanan United States	5	379 0.6×	216 0.6×	136 0.7×	35 0.2×	73 0.9×	8	470
Gordon T. Hamachi United States	7	295 0.5×	221 0.6×	85 0.4×	41 0.3×	33 0.4×	8	406
Narendra Shenoy United States	19	852 1.3×	781 2.0×	150 0.8×	21 0.1×	198 2.5×	41	1.0k
Robert N. Mayo United States	10	294 0.4×	284 0.7×	127 0.7×	31 0.2×	36 0.5×	15	475
Kei-Yong Khoo United States	13	608 0.9×	403 1.0×	156 0.8×	51 0.3×	76 0.9×	51	717
J.A.G. Jess Netherlands	20	717 1.1×	768 2.0×	181 0.9×	55 0.4×	107 1.3×	77	1.0k

Countries citing papers authored by C. L. Liu

Since Specialization

Citations

This map shows the geographic impact of C. L. Liu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. L. Liu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. L. Liu more than expected).

Fields of papers citing papers by C. L. Liu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. L. Liu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. L. Liu. The network helps show where C. L. Liu may publish in the future.

Co-authorship network of co-authors of C. L. Liu

This figure shows the co-authorship network connecting the top 25 collaborators of C. L. Liu. A scholar is included among the top collaborators of C. L. Liu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. L. Liu. C. L. Liu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

1.

Pan, Peichen & C. L. Liu. (1998). Optimal clock period FPGA technology mapping for sequential circuits. ACM Transactions on Design Automation of Electronic Systems. 3(3). 437–462. 16 indexed citations

2.

Liu, C. L., et al.. (1997). Low power logic synthesis for XOR based circuits. International Conference on Computer Aided Design. 570–574. 22 indexed citations

3.

Leong, Wai Yie, et al.. (1997). Low power multiplexer decomposition. 269–274. 20 indexed citations

4.

Liu, C. L., et al.. (1997). Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits. 1 indexed citations

5.

Wong, Chris K.C., et al.. (1997). Routing for symmetric FPGAs and FPICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16(1). 20–31. 10 indexed citations

6.

Kim, Taewhan & C. L. Liu. (1996). An integrated algorithm for incremental data path synthesis. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 12(3). 265–285. 1 indexed citations

7.

Pan, Peichen, Weiping Shi, & C. L. Liu. (1996). Area minimization for hierarchical floorplans. Algorithmica. 15(6). 550–571. 8 indexed citations

8.

Pan, Peichen & C. L. Liu. (1995). Partial scan with pre-selected scan signals. 189–194. 2 indexed citations

9.

Wong, C. K., et al.. (1993). Routing for symmetric FPGAs and FPICs. International Conference on Computer Aided Design. 16(1). 486–490. 19 indexed citations

10.

Pan, Peichen & C. L. Liu. (1992). Area minimization for general floorplans. International Conference on Computer Aided Design. 1992. 606–609. 2 indexed citations

11.

Cong, Jason, Bryan Preas, & C. L. Liu. (1990). General models and algorithms for over-the-cell routing in standard cell design. 709–715. 36 indexed citations

12.

Libeskind-Hadas, Ran & C. L. Liu. (1989). Solutions to the module orientation and rotation problems by neural computation networks. 400–405. 27 indexed citations

13.

Wong, Martin D. F., et al.. (1989). An enhanced bottom-up algorithm for floorplan design. Integration. 7(2). 189–201. 7 indexed citations

14.

Wong, Martin D. F. & C. L. Liu. (1989). Floorplan design of VLSI circuits. Algorithmica. 4(1-4). 263–291. 57 indexed citations

15.

Wong, Martin D. F., Wai Yie Leong, & C. L. Liu. (1988). Simulated Annealing for VLSI Design. 136 indexed citations

16.

Wong, Martin D. F., et al.. (1987). NEW APPROACH TO THE THREE LAYER CHANNEL ROUTING PROBLEM.. 378–381. 21 indexed citations

17.

Wong, Martin D. F. & C. L. Liu. (1987). Array optimization for VLSI synthesis. 537–543. 3 indexed citations

18.

Leong, Wai Yie & C. L. Liu. (1987). Algorithms for permutation channel routing. Integration. 5(1). 17–45. 2 indexed citations

19.

Wong, Martin D. F. & C. L. Liu. (1986). A New Algorithm for Floorplan Design. Design Automation Conference. 101–107. 379 indexed citations

20.

Leong, Wai Yie, Martin D. F. Wong, & C. L. Liu. (1985). SIMULATED-ANNEALING CHANNEL ROUTER.. 226–228. 28 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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