Wai-Shing Luk

593 total citations
31 papers, 420 citations indexed

About

Wai-Shing Luk is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Wai-Shing Luk has authored 31 papers receiving a total of 420 indexed citations (citations by other indexed papers that have themselves been cited), including 23 papers in Electrical and Electronic Engineering, 19 papers in Hardware and Architecture and 5 papers in Computer Networks and Communications. Recurrent topics in Wai-Shing Luk's work include VLSI and FPGA Design Techniques (15 papers), Advancements in Photolithography Techniques (10 papers) and Parallel Computing and Optimization Techniques (9 papers). Wai-Shing Luk is often cited by papers focused on VLSI and FPGA Design Techniques (15 papers), Advancements in Photolithography Techniques (10 papers) and Parallel Computing and Optimization Techniques (9 papers). Wai-Shing Luk collaborates with scholars based in China, United States and Hong Kong. Wai-Shing Luk's co-authors include Tien-Tsin Wong, Tien‐Tsin Wong, Pheng‐Ann Heng, Xuan Zeng, Changhao Yan, Hai Zhou, Ye Zhang, Dian Zhou, David Z. Pan and Jun Tao and has published in prestigious journals such as IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Wai-Shing Luk

23 papers receiving 402 citations

Peers

Countries citing papers authored by Wai-Shing Luk

Since Specialization

Citations

This map shows the geographic impact of Wai-Shing Luk's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Wai-Shing Luk with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Wai-Shing Luk more than expected).

Fields of papers citing papers by Wai-Shing Luk

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Wai-Shing Luk. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Wai-Shing Luk. The network helps show where Wai-Shing Luk may publish in the future.

Co-authorship network of co-authors of Wai-Shing Luk

This figure shows the co-authorship network connecting the top 25 collaborators of Wai-Shing Luk. A scholar is included among the top collaborators of Wai-Shing Luk based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Wai-Shing Luk. Wai-Shing Luk is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution 2025 ·(unknown), Wai-Shing Luk, Lingli Wang	0
2	CDE: A Novel CGRA Development Environment with Fast Design Space Exploration Framework 2024 ·(unknown), (unknown), Jide Zhang, (unknown), (unknown), Wai-Shing Luk, Wenbo Yin, Lingli Wang	0
3	CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design 2024 ·(unknown), (unknown), (unknown), (unknown), (unknown), Wai-Shing Luk, Lingli Wang	1
4	FPGA Routing Optimization Based on Multi-Level MUX Architecture 2024 ·(unknown), (unknown), Wai-Shing Luk, Hao Zhou, Lingli Wang	0
5	Iterative and Verifiable Retiming for FPGA Performance Optimization 2023 ·Kaixiang Zhu, Hao Zhou, Wai-Shing Luk, Jun Tao, Lingli Wang	0
6	A Fast Timing Analysis and Optimization for Latch-Based Circuits 2022 ·Kaixiang Zhu, (unknown), Wai-Shing Luk, Lingli Wang, Jun Tao	0
7	FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA 2020 ·IEEE Transactions on Parallel and Distributed Systems ·(unknown), (unknown), (unknown), Wenbo Yin, Wai-Shing Luk, Lingli Wang, (unknown), (unknown), (unknown), (unknown), (unknown)	9
8	Scalable Multi-Session TCP Offload Engine for Latency-Sensitive Applications 2020 ·Jingbo Gao, Wenbo Yin, Wai-Shing Luk, Lingli Wang	0
9	Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization 2018 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng	0
10	Network flow based cut redistribution and insertion for advanced 1D layout design 2017 ·Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng	1
11	An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation 2017 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown), Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng	4
12	Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography 2015 ·ACM Transactions on Design Automation of Electronic Systems ·Ye Zhang, Wai-Shing Luk, (unknown), Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng	1
13	Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography 2015 ·(unknown), Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou	6
14	An efficient algorithm for multi-domain clock skew scheduling 2011 ·(unknown), Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng	2
15	Fast and lossless graph division method for layout decomposition using SPQR-tree 2010 ·Wai-Shing Luk, (unknown)	10
16	Characterizing Intra-Die Spatial Correlation Using Spectral Density Method 2008 ·(unknown), Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng	4
17	Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays 2008 ·Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, (unknown), Wei Cai, Jia Ni	11
18	WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design 2007 ·Peng Zhang, Wai-Shing Luk, Yu Song, (unknown), (unknown), Xuan Zeng	6
19	Two new quorum based algorithms for distributed mutual exclusion 2002 ·Wai-Shing Luk, Tien-Tsin Wong	115
20	Sampling with Hammersley and Halton Points 1997 ·Journal of Graphics Tools ·Tien‐Tsin Wong, Wai-Shing Luk, Pheng‐Ann Heng	175

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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