Yarui Peng

766 total citations
55 papers, 480 citations indexed

About

Yarui Peng is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Yarui Peng has authored 55 papers receiving a total of 480 indexed citations (citations by other indexed papers that have themselves been cited), including 52 papers in Electrical and Electronic Engineering, 6 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in Yarui Peng's work include 3D IC and TSV technologies (35 papers), Silicon Carbide Semiconductor Technologies (18 papers) and Electromagnetic Compatibility and Noise Suppression (17 papers). Yarui Peng is often cited by papers focused on 3D IC and TSV technologies (35 papers), Silicon Carbide Semiconductor Technologies (18 papers) and Electromagnetic Compatibility and Noise Suppression (17 papers). Yarui Peng collaborates with scholars based in United States, China and United Kingdom. Yarui Peng's co-authors include Sung Kyu Lim, Taigon Song, H. Alan Mantooth, Quang Trung Le, Dusan Petranovic, Chang Liu, Alan Mantooth, Moongon Jung, Yang Wan and Balaji Narayanasamy and has published in prestigious journals such as IEEE Transactions on Power Electronics, BMJ Open and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Yarui Peng

51 papers receiving 467 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Yarui Peng United States 13 440 72 60 33 22 55 480
Debendra Mallik United States 7 339 0.8× 75 1.0× 41 0.7× 45 1.4× 18 0.8× 11 392
Joo-Sun Choi South Korea 9 278 0.6× 38 0.5× 29 0.5× 19 0.6× 19 0.9× 13 301
Chin-Chi Teng United States 11 506 1.1× 243 3.4× 31 0.5× 13 0.4× 6 0.3× 26 555
Cheng Qian China 9 221 0.5× 52 0.7× 74 1.2× 39 1.2× 16 0.7× 41 369
Sudhanshu Khanna United States 9 346 0.8× 99 1.4× 36 0.6× 54 1.6× 26 1.2× 21 376
Jianping Xu China 11 350 0.8× 27 0.4× 57 0.9× 36 1.1× 35 1.6× 54 408
Ching-Han Tsai United States 9 339 0.8× 100 1.4× 42 0.7× 19 0.6× 6 0.3× 12 395
Sudhir S. Kudva United States 9 296 0.7× 43 0.6× 24 0.4× 26 0.8× 15 0.7× 23 317
Mei-Fang Chiang Japan 7 318 0.7× 159 2.2× 106 1.8× 49 1.5× 31 1.4× 13 372

Countries citing papers authored by Yarui Peng

Since Specialization
Citations

This map shows the geographic impact of Yarui Peng's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yarui Peng with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yarui Peng more than expected).

Fields of papers citing papers by Yarui Peng

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yarui Peng. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yarui Peng. The network helps show where Yarui Peng may publish in the future.

Co-authorship network of co-authors of Yarui Peng

This figure shows the co-authorship network connecting the top 25 collaborators of Yarui Peng. A scholar is included among the top collaborators of Yarui Peng based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yarui Peng. Yarui Peng is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Huitink, David, et al.. (2023). Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules. Journal of Microelectronics and Electronic Packaging. 20(4).
2.
Saadatizadeh, Zahra, et al.. (2023). Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth. 1–6. 1 indexed citations
3.
Le, Quang Trung, et al.. (2022). PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules. IEEE Transactions on Power Electronics. 38(4). 4698–4713. 14 indexed citations
4.
Le, Quang Trung, et al.. (2022). Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses. IEEE Journal of Emerging and Selected Topics in Power Electronics. 11(6). 5613–5625. 6 indexed citations
5.
Peng, Yarui, et al.. (2022). Configurational Paths to Higher Efficiency in County Hospital: Evidence From Qualitative Comparative Analysis. Frontiers in Public Health. 10. 918571–918571. 6 indexed citations
6.
Huitink, David, et al.. (2022). Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth. 2022 IEEE Energy Conversion Congress and Exposition (ECCE). 1–8. 2 indexed citations
7.
Le, Quang Trung, et al.. (2021). PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules. IEEE Transactions on Power Electronics. 36(8). 8919–8933. 28 indexed citations
8.
Peng, Yarui, et al.. (2021). Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design. IEEE Transactions on Components Packaging and Manufacturing Technology. 11(5). 715–726. 5 indexed citations
9.
Ho, Tsung-Yi, et al.. (2021). Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization. 1–4. 1 indexed citations
10.
11.
Le, Quang Trung, et al.. (2021). PowerSynth Integrated CAD flow for High Density Power Modules. 1–6. 3 indexed citations
12.
Peng, Yarui, et al.. (2020). Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. 351–356. 17 indexed citations
13.
Peng, Yarui, et al.. (2020). Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study. 277–282. 1 indexed citations
14.
Le, Quang Trung, et al.. (2020). Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization. 1984–1991. 6 indexed citations
15.
16.
17.
Petranovic, Dusan, et al.. (2020). Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design. 1–8. 10 indexed citations
18.
Peng, Yarui, Dusan Petranovic, & Sung Kyu Lim. (2017). Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging. 1–3. 4 indexed citations
19.
Song, Taigon, Moongon Jung, Yang Wan, Yarui Peng, & Sung Kyu Lim. (2015). 3D IC power benefit study under practical design considerations. 335–338. 2 indexed citations
20.
Peng, Yarui, Taigon Song, Dusan Petranovic, & Sung Kyu Lim. (2014). Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33(12). 1900–1913. 30 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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