Mei-Fang Chiang

434 total citations
13 papers, 372 citations indexed

About

Mei-Fang Chiang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Automotive Engineering. According to data from OpenAlex, Mei-Fang Chiang has authored 13 papers receiving a total of 372 indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Electrical and Electronic Engineering, 9 papers in Hardware and Architecture and 1 paper in Automotive Engineering. Recurrent topics in Mei-Fang Chiang's work include VLSI and FPGA Design Techniques (7 papers), Low-power high-performance VLSI design (5 papers) and VLSI and Analog Circuit Testing (5 papers). Mei-Fang Chiang is often cited by papers focused on VLSI and FPGA Design Techniques (7 papers), Low-power high-performance VLSI design (5 papers) and VLSI and Analog Circuit Testing (5 papers). Mei-Fang Chiang collaborates with scholars based in Japan, Taiwan and China. Mei-Fang Chiang's co-authors include Shuangchen Li, Huazhong Yang, Yongpan Liu, Yiqun Wang, Daming Zhang, Huang-Yu Chen, Yao‐Wen Chang, Bo Zhao, Yiqun Wang and Xiaobo Sharon Hu and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and NTUR (臺灣機構典藏).

In The Last Decade

Mei-Fang Chiang

11 papers receiving 364 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Mei-Fang Chiang Japan	7	318	159	106	49	34	13	372
Yarui Peng United States	13	440 1.4×	72 0.5×	60 0.6×	33 0.7×	10 0.3×	55	480
P. Morrow United States	3	464 1.5×	245 1.5×	271 2.6×	25 0.5×	36 1.1×	3	584
R. Franch United States	15	588 1.8×	224 1.4×	74 0.7×	18 0.4×	63 1.9×	44	663
Paul A. Reed United States	3	337 1.1×	245 1.5×	263 2.5×	16 0.3×	11 0.3×	5	458
Sudhanshu Khanna United States	9	346 1.1×	99 0.6×	36 0.3×	54 1.1×	52 1.5×	21	376
Clair Webb United States	9	668 2.1×	355 2.2×	354 3.3×	17 0.3×	43 1.3×	16	807
Brent Goplen United States	9	817 2.6×	174 1.1×	242 2.3×	35 0.7×	30 0.9×	10	855
Robert Sankman United States	5	301 0.9×	79 0.5×	42 0.4×	21 0.4×	54 1.6×	8	336
Jianping Xu China	11	350 1.1×	27 0.2×	57 0.5×	36 0.7×	42 1.2×	54	408

Countries citing papers authored by Mei-Fang Chiang

Since Specialization

Citations

This map shows the geographic impact of Mei-Fang Chiang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mei-Fang Chiang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mei-Fang Chiang more than expected).

Fields of papers citing papers by Mei-Fang Chiang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mei-Fang Chiang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mei-Fang Chiang. The network helps show where Mei-Fang Chiang may publish in the future.

Co-authorship network of co-authors of Mei-Fang Chiang

This figure shows the co-authorship network connecting the top 25 collaborators of Mei-Fang Chiang. A scholar is included among the top collaborators of Mei-Fang Chiang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Mei-Fang Chiang. Mei-Fang Chiang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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13 of 13 papers shown

Wang, Yiqun, Yongpan Liu, Shuangchen Li, et al.. (2013). PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(7). 1491–1505. 43 indexed citations

Wang, Yiqun, et al.. (2012). A compression-based area-efficient recovery architecture for nonvolatile processors. Design, Automation, and Test in Europe. 1519–1524. 40 indexed citations

Chiang, Mei-Fang. (2012). Retirement Consumption Behavior: Evidence from HRS CAMS 2001-2009. OhioLink ETD Center (Ohio Library and Information Network). 1 indexed citations

Wang, Yiqun, Yongpan Liu, Shuangchen Li, et al.. (2012). A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. 149–152. 160 indexed citations

Wang, Yiqun, Yongpan Liu, Yumeng Liu, et al.. (2012). A compression-based area-efficient recovery architecture for nonvolatile processors. 1519–1524. 21 indexed citations

Chiang, Mei-Fang, et al.. (2009). Register placement for high-performance circuits. Design, Automation, and Test in Europe. 1470–1475. 2 indexed citations

Shen, Jianwei, Mei-Fang Chiang, Song Chen, Wei Guo, & Takeshi Yoshimura. (2009). Redundant via allocation for layer partition-based redundant via insertion. 734–737. 1 indexed citations

Guo, Wei, Song Chen, Mei-Fang Chiang, Jianwei Shen, & Takeshi Yoshimura. (2009). Convex-cost flow based redundant-via insertion with density-balance consideration. 1280–1283.

Chiang, Mei-Fang, Takuya Okamoto, & Takeshi Yoshimura. (2009). Register placement for high-performance circuits. 1470–1475. 2 indexed citations

10.

Chen, Huang-Yu, et al.. (2008). Full-Chip Routing Considering Double-Via Insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(5). 844–857. 56 indexed citations

11.

Chen, Huang-Yu, et al.. (2006). Novel full-chip gridless routing considering double-via insertion. NTUR (臺灣機構典藏). 755–755. 35 indexed citations

12.

Chen, Huang-Yu, et al.. (2006). Novel full-chip gridless routing considering double-via insertion. Proceedings - ACM IEEE Design Automation Conference. 21. 755–760. 10 indexed citations

13.

Chiang, Mei-Fang, et al.. (1991). Analogue adaptive neural network circuit. IEE Proceedings G Circuits Devices and Systems. 138(6). 717–717. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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