N. Demassieux

546 total citations
28 papers, 285 citations indexed

About

N. Demassieux is a scholar working on Signal Processing, Electrical and Electronic Engineering and Computer Vision and Pattern Recognition. According to data from OpenAlex, N. Demassieux has authored 28 papers receiving a total of 285 indexed citations (citations by other indexed papers that have themselves been cited), including 11 papers in Signal Processing, 11 papers in Electrical and Electronic Engineering and 10 papers in Computer Vision and Pattern Recognition. Recurrent topics in N. Demassieux's work include Advanced Data Compression Techniques (7 papers), Digital Filter Design and Implementation (7 papers) and Analog and Mixed-Signal Circuit Design (7 papers). N. Demassieux is often cited by papers focused on Advanced Data Compression Techniques (7 papers), Digital Filter Design and Implementation (7 papers) and Analog and Mixed-Signal Circuit Design (7 papers). N. Demassieux collaborates with scholars based in France and Thailand. N. Demassieux's co-authors include P. Pirsch, Emmanuel Boutillon, K. Dejhan, Henri Maı̂tre, M. Saint-Paul, Matthias Müller, Yves Mathieu, Denis Roux and Gérard Chollet and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Consumer Electronics.

In The Last Decade

N. Demassieux

20 papers receiving 255 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
N. Demassieux France 6 186 164 84 61 50 28 285
O.T.-C. Chen Taiwan 9 98 0.5× 153 0.9× 196 2.3× 64 1.0× 18 0.4× 33 376
Cláudio Diniz Brazil 12 287 1.5× 262 1.6× 170 2.0× 54 0.9× 16 0.3× 60 442
Hung-Chi Fang Taiwan 12 452 2.4× 467 2.8× 78 0.9× 41 0.7× 54 1.1× 33 556
Yen‐Tai Lai Taiwan 9 49 0.3× 64 0.4× 168 2.0× 88 1.4× 58 1.2× 38 270
Didier J. LeGall United States 5 213 1.1× 313 1.9× 35 0.4× 20 0.3× 49 1.0× 10 372
T. Takayanagi Japan 9 77 0.4× 76 0.5× 167 2.0× 100 1.6× 55 1.1× 19 266
Ercan Kalalı Türkiye 14 389 2.1× 373 2.3× 46 0.5× 39 0.6× 15 0.3× 32 448
F.W. Hoeksema Netherlands 8 131 0.7× 131 0.8× 121 1.4× 20 0.3× 134 2.7× 35 300
Chen‐Han Tsai Taiwan 8 421 2.3× 463 2.8× 58 0.7× 49 0.8× 50 1.0× 18 533
José Luís Güntzel Brazil 9 126 0.7× 115 0.7× 166 2.0× 112 1.8× 18 0.4× 80 287

Countries citing papers authored by N. Demassieux

Since Specialization
Citations

This map shows the geographic impact of N. Demassieux's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by N. Demassieux with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites N. Demassieux more than expected).

Fields of papers citing papers by N. Demassieux

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by N. Demassieux. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by N. Demassieux. The network helps show where N. Demassieux may publish in the future.

Co-authorship network of co-authors of N. Demassieux

This figure shows the co-authorship network connecting the top 25 collaborators of N. Demassieux. A scholar is included among the top collaborators of N. Demassieux based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with N. Demassieux. N. Demassieux is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Demassieux, N., et al.. (2005). VLSI Architecture for a one chip video median filter. 10. 1001–1004. 2 indexed citations
2.
Demassieux, N., et al.. (2003). A 10 MHz (255, 223) Reed-Solomon decoder. 17.6/1–17.6/4.
3.
Demassieux, N., et al.. (2003). A single chip VLSI architecture for a real time stereo vision processor. 1965–1968. 2 indexed citations
4.
Demassieux, N., et al.. (2003). A one chip VLSI for real time two-dimensional discrete cosine transform. 701–704. 7 indexed citations
5.
6.
Mathieu, Yves, et al.. (2002). A real-time multi-kernel picture convolver. 17.8/1–17.8/4. 1 indexed citations
7.
Demassieux, N., et al.. (2002). A new VLSI architecture for large kernel real time convolution. International Conference on Acoustics, Speech, and Signal Processing. 921–924.
8.
Demassieux, N., et al.. (2002). Optimal VLSI architecture for distributed arithmetic-based algorithms. ii. II/509–II/512. 7 indexed citations
9.
Demassieux, N.. (2002). Au-delà de la 3G : les objets communicants ?. -(8). 71–71. 1 indexed citations
10.
Demassieux, N., et al.. (2002). Distributed architecture for data acquisition: a generic model. 2. 1180–1185. 4 indexed citations
11.
Boutillon, Emmanuel & N. Demassieux. (2002). A generalized precompiling scheme for surviving path memory management in Viterbi decoders. 1993 IEEE International Symposium on Circuits and Systems. 1579–1582. 3 indexed citations
12.
Demassieux, N., et al.. (1996). A Generic Smart Sensor Model for Real-time Distributed Data Acquisition Systems.. Parallel and Distributed Processing Techniques and Applications. 329–340. 2 indexed citations
13.
Demassieux, N., et al.. (1996). <title>Generic model for smart-sensor-based data acquisition system</title>. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 2718. 279–290. 2 indexed citations
14.
Pirsch, P., et al.. (1995). VLSI architectures for video compression-a survey. Proceedings of the IEEE. 83(2). 220–246. 203 indexed citations
15.
Demassieux, N., et al.. (1993). Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing. IEEE International Conference on Acoustics Speech and Signal Processing. 393–396 vol.1. 1 indexed citations
16.
Demassieux, N., et al.. (1991). A versatile architecture for VLSI implementation of the Viterbi algorithm. 1101–1104 vol.2. 8 indexed citations
17.
Demassieux, N., et al.. (1991). DCT architectures for HDTV. 1360. 196–199 vol.1. 5 indexed citations
18.
Dejhan, K., et al.. (1990). Design of a low-power 32 K CMOS programmable delay-line memory. IEEE Journal of Solid-State Circuits. 25(1). 234–238. 4 indexed citations
19.
Dejhan, K., et al.. (1989). A new high-performance programmable delay line IC. IEEE Transactions on Consumer Electronics. 35(4). 893–900. 5 indexed citations
20.
Demassieux, N., et al.. (1988). VLSI Architectures For Image Filtering. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 1001. 1108–1108. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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