Sresta Valasa

462 total citations
32 papers, 284 citations indexed

About

Sresta Valasa is a scholar working on Electrical and Electronic Engineering, Materials Chemistry and Atomic and Molecular Physics, and Optics. According to data from OpenAlex, Sresta Valasa has authored 32 papers receiving a total of 284 indexed citations (citations by other indexed papers that have themselves been cited), including 30 papers in Electrical and Electronic Engineering, 5 papers in Materials Chemistry and 2 papers in Atomic and Molecular Physics, and Optics. Recurrent topics in Sresta Valasa's work include Semiconductor materials and devices (27 papers), Advancements in Semiconductor Devices and Circuit Design (24 papers) and Ferroelectric and Negative Capacitance Devices (11 papers). Sresta Valasa is often cited by papers focused on Semiconductor materials and devices (27 papers), Advancements in Semiconductor Devices and Circuit Design (24 papers) and Ferroelectric and Negative Capacitance Devices (11 papers). Sresta Valasa collaborates with scholars based in India and Switzerland. Sresta Valasa's co-authors include Shubham Tayal, Laxman Raju Thoutam, Narendar Vadthiya, Sandip Bhattacharya, J. Ajayan, Biswajit Jena, Keshav Kaushik, Satish Maheshwaram, Phanikrishna Thota and Hitesh Borkar and has published in prestigious journals such as Journal of Physics D Applied Physics, IEEE Transactions on Electron Devices and IEEE Transactions on Dielectrics and Electrical Insulation.

In The Last Decade

Sresta Valasa

28 papers receiving 249 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Sresta Valasa India	12	271	46	22	7	6	32	284
Sanghoon Baek South Korea	8	291 1.1×	14 0.3×	16 0.7×	5 0.7×	9 1.5×	12	310
E. Capogreco Belgium	11	199 0.7×	30 0.7×	28 1.3×	7 1.0×	20 3.3×	26	204
Shivendra Singh Parihar India	7	197 0.7×	32 0.7×	25 1.1×	6 0.9×	15 2.5×	28	220
Ping-Chuan Chiang Taiwan	12	440 1.6×	48 1.0×	11 0.5×	10 1.4×	21 3.5×	21	448
Josef Watts United States	11	330 1.2×	37 0.8×	16 0.7×	4 0.6×	11 1.8×	28	345
Shien-Yang Wu Taiwan	7	165 0.6×	19 0.4×	7 0.3×	6 0.9×	4 0.7×	12	183
Mahsa Mehrad Iran	16	462 1.7×	33 0.7×	32 1.5×	10 1.4×	14 2.3×	30	470
S. Geißler United States	10	258 1.0×	17 0.4×	17 0.8×	7 1.0×	8 1.3×	19	272
Mohan V. Dunga United States	12	362 1.3×	42 0.9×	7 0.3×	4 0.6×	14 2.3×	27	373
Jeng-Liang Tsai United States	9	320 1.2×	16 0.3×	7 0.3×	7 1.0×	4 0.7×	16	336

Countries citing papers authored by Sresta Valasa

Since Specialization

Citations

This map shows the geographic impact of Sresta Valasa's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sresta Valasa with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sresta Valasa more than expected).

Fields of papers citing papers by Sresta Valasa

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sresta Valasa. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sresta Valasa. The network helps show where Sresta Valasa may publish in the future.

Co-authorship network of co-authors of Sresta Valasa

This figure shows the co-authorship network connecting the top 25 collaborators of Sresta Valasa. A scholar is included among the top collaborators of Sresta Valasa based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sresta Valasa. Sresta Valasa is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Thota, Phanikrishna, et al.. (2025). Physical insights into optimization of dual metal gate junctionless tree-shaped FETs at sub-5 nm technology node: device to circuit approach. Physica Scripta. 100(6). 65970–65970.

Valasa, Sresta, et al.. (2025). Role of Dielectric-Semiconductor Interface Traps in Multilayer MoS₂ FinFETs: An Investigation From Device to Circuit. IEEE Transactions on Dielectrics and Electrical Insulation. 33(1). 149–157. 1 indexed citations

Valasa, Sresta, et al.. (2025). Interface trap dynamics and thermal effects in novel junctionless dual gate inverted-U-shaped FinFETs for sub-5 nm node: device to circuit level implementation. Journal of Physics D Applied Physics. 58(13). 135114–135114. 1 indexed citations

Valasa, Sresta, et al.. (2025). Design Insights of Multilayer MoS₂ Fin-Shaped FETs for Digital and Analog/RF Applications. ACS Applied Electronic Materials. 7(15). 6747–6760.

Valasa, Sresta, et al.. (2024). Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics. Materials Science in Semiconductor Processing. 173. 108116–108116. 24 indexed citations

Valasa, Sresta, et al.. (2024). Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications. IEEE Transactions on Dielectrics and Electrical Insulation. 32(2). 769–778. 7 indexed citations

Valasa, Sresta, et al.. (2024). Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy—A Dielectric Perspective. IEEE Transactions on Dielectrics and Electrical Insulation. 32(4). 1997–2004. 3 indexed citations

Valasa, Sresta, et al.. (2024). Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications. IEEE Transactions on Device and Materials Reliability. 25(1). 119–127. 2 indexed citations

Valasa, Sresta, et al.. (2024). Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance. ECS Journal of Solid State Science and Technology. 13(10). 103007–103007. 2 indexed citations

10.

Valasa, Sresta, et al.. (2024). Insights Into Substrate Dielectric Engineering of Monolayer MoS₂ FET: Digital/Analog/RF Perspective to Circuit Implementation. IEEE Transactions on Dielectrics and Electrical Insulation. 32(3). 1549–1556. 3 indexed citations

11.

Valasa, Sresta, et al.. (2024). Study of HeavyIon Irradiation Effects in FinFETs at Sub-5 nm Technology Node: Reliability Perspective. 1–5.

12.

Valasa, Sresta, et al.. (2023). Design Considerations into Circuit Applications for Structurally Optimised FinFET. ECS Journal of Solid State Science and Technology. 12(12). 123007–123007. 3 indexed citations

13.

Valasa, Sresta, et al.. (2023). Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective. ECS Journal of Solid State Science and Technology. 13(1). 13002–13002. 4 indexed citations

14.

Valasa, Sresta, et al.. (2023). Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices. ECS Journal of Solid State Science and Technology. 12(11). 113012–113012. 3 indexed citations

15.

Valasa, Sresta, et al.. (2023). Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications. ECS Journal of Solid State Science and Technology. 12(9). 93007–93007. 16 indexed citations

16.

Valasa, Sresta, Shubham Tayal, & Laxman Raju Thoutam. (2022). Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node. ECS Journal of Solid State Science and Technology. 11(9). 93006–93006. 11 indexed citations

17.

Valasa, Sresta, Shubham Tayal, & Laxman Raju Thoutam. (2022). Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node. ECS Journal of Solid State Science and Technology. 11(4). 41008–41008. 17 indexed citations

18.

Tayal, Shubham, et al.. (2022). Impact of Channel Thickness on the Performance of JL-DG MOSFET based NAND, NOR, and NOT Logic Gates. 1–4. 2 indexed citations

19.

Valasa, Sresta, Shubham Tayal, & Laxman Raju Thoutam. (2022). Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications. Silicon. 14(16). 10347–10356. 20 indexed citations

20.

Tayal, Shubham, Sresta Valasa, Sandip Bhattacharya, et al.. (2022). Investigation of Nanosheet-FET Based Logic Gates at Sub-7 nm Technology Node for Digital IC Applications. Silicon. 14(18). 12261–12267. 21 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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