Chingwei Yeh

777 total citations
55 papers, 571 citations indexed

About

Chingwei Yeh is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Chingwei Yeh has authored 55 papers receiving a total of 571 indexed citations (citations by other indexed papers that have themselves been cited), including 41 papers in Electrical and Electronic Engineering, 23 papers in Hardware and Architecture and 10 papers in Computer Networks and Communications. Recurrent topics in Chingwei Yeh's work include Low-power high-performance VLSI design (31 papers), VLSI and FPGA Design Techniques (20 papers) and VLSI and Analog Circuit Testing (11 papers). Chingwei Yeh is often cited by papers focused on Low-power high-performance VLSI design (31 papers), VLSI and FPGA Design Techniques (20 papers) and VLSI and Analog Circuit Testing (11 papers). Chingwei Yeh collaborates with scholars based in Taiwan, United States and Czechia. Chingwei Yeh's co-authors include Jinn‐Shyan Wang, Chung‐Kuan Cheng, Chih‐Chung Lin, Wen‐Tien Tsai, Ting-Ting Y. Lin, Tao Lin, Chung-Kuan Cheng, Shih-Chieh Chang, Shih-Hsin Chen and Hung‐Yuan Li and has published in prestigious journals such as Renewable and Sustainable Energy Reviews, IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems for Video Technology.

In The Last Decade

Chingwei Yeh

53 papers receiving 537 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Chingwei Yeh Taiwan	14	399	272	107	102	47	55	571
Jianli Chen China	13	383 1.0×	264 1.0×	44 0.4×	31 0.3×	29 0.6×	93	518
Ranjeet Kumar United States	9	372 0.9×	95 0.3×	53 0.5×	53 0.5×	27 0.6×	12	510
A. Albicki United States	10	449 1.1×	127 0.5×	43 0.4×	68 0.7×	38 0.8×	37	479
Shiyan Hu United States	12	343 0.9×	123 0.5×	118 1.1×	59 0.6×	10 0.2×	37	420
Xuan Dong United States	13	279 0.7×	25 0.1×	195 1.8×	93 0.9×	10 0.2×	37	525
Jianming Yan China	10	131 0.3×	222 0.8×	210 2.0×	12 0.1×	12 0.3×	17	429
D.C. da Silva Brazil	9	219 0.5×	51 0.2×	280 2.6×	36 0.4×	16 0.3×	23	388
R. Scarsi Italy	14	595 1.5×	312 1.1×	242 2.3×	20 0.2×	45 1.0×	33	752
Zhigang Sun China	13	87 0.2×	153 0.6×	438 4.1×	21 0.2×	27 0.6×	69	535
Andy A. Hwang Canada	7	237 0.6×	168 0.6×	300 2.8×	12 0.1×	6 0.1×	10	484

Countries citing papers authored by Chingwei Yeh

Since Specialization

Citations

This map shows the geographic impact of Chingwei Yeh's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chingwei Yeh with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chingwei Yeh more than expected).

Fields of papers citing papers by Chingwei Yeh

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chingwei Yeh. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chingwei Yeh. The network helps show where Chingwei Yeh may publish in the future.

Co-authorship network of co-authors of Chingwei Yeh

This figure shows the co-authorship network connecting the top 25 collaborators of Chingwei Yeh. A scholar is included among the top collaborators of Chingwei Yeh based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chingwei Yeh. Chingwei Yeh is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Chen, Po-Han, Shu‐Chin Lin, Ching‐Jen Wang, et al.. (2024). Performance Evaluation of MEMS Vibration Sensors for Throat Microphones. 1–4. 1 indexed citations

Lin, Kuan‐Han, et al.. (2023). A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Transactions on Circuits & Systems II Express Briefs. 70(12). 4564–4568. 1 indexed citations

Lin, Tay–Jyi, Youjia Hu, Wei-Cheng Hsu, et al.. (2022). A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. 7–8. 3 indexed citations

Yeh, Chingwei, et al.. (2013). Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. 426–427. 8 indexed citations

Chen, Tien-Fu, et al.. (2011). Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. ACM Transactions on Architecture and Code Optimization. 8(3). 1–27. 1 indexed citations

Wang, Jinn‐Shyan, et al.. (2011). RSCE-aware ultra-low-voltage 40-nm CMOS circuits. 15. 131–134. 1 indexed citations

Wang, Jinn‐Shyan, et al.. (2008). High-Speed and Low-Power Design Techniques for TCAM Macros. IEEE Journal of Solid-State Circuits. 43(2). 530–540. 44 indexed citations

Wang, Jinn‐Shyan, et al.. (2006). TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. 577–586. 17 indexed citations

Chen, S-H, et al.. (2006). Timing driven power gating. Proceedings - ACM IEEE Design Automation Conference. 121–124. 3 indexed citations

10.

Li, Hung‐Yuan, et al.. (2005). An AND-type match-line scheme for energy-efficient content addressable memories. 464–466. 23 indexed citations

11.

Li, Hung‐Yuan, et al.. (2005). Design techniques for single-low-V/sub DD/ CMOS systems. IEEE Journal of Solid-State Circuits. 40(5). 1157–1165. 9 indexed citations

12.

Yeh, Chingwei, et al.. (2003). Power reduction through iterative gate sizing and voltage scaling. 1. 246–249. 1 indexed citations

13.

Chang, Shih-Chieh, et al.. (2002). On removing multiple redundancies in combinational circuits. 738–742. 3 indexed citations

14.

Wang, Jinn‐Shyan, et al.. (2001). Analysis and design of high-speed and low-power CMOS PLAs. IEEE Journal of Solid-State Circuits. 36(8). 1250–1262. 26 indexed citations

15.

Jone, Wen-Ben, et al.. (2001). An adaptive path selection method for delay testing. IEEE Transactions on Instrumentation and Measurement. 50(5). 1109–1118. 8 indexed citations

16.

Yeh, Chingwei, et al.. (1999). Layout techniques supporting the use of dual supply voltages for cell-based designs. 62–67. 30 indexed citations

17.

Yeh, Chingwei, et al.. (1996). On the integration of partitioning and global routing for rectilinear placement problems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15(1). 83–91. 1 indexed citations

18.

Yeh, Chingwei, Chung-Kuan Cheng, & Tao Lin. (1995). Circuit clustering using a stochastic flow injection method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14(2). 154–162. 14 indexed citations

19.

Yeh, Chingwei, Chung‐Kuan Cheng, & Tao Lin. (1994). A general purpose, multiple-way partitioning algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13(12). 1480–1488. 18 indexed citations

20.

Yeh, Chingwei, Chung‐Kuan Cheng, & Ting-Ting Y. Lin. (1992). A probabilistic multicommodity-flow solution to circuit clustering problems. International Conference on Computer Aided Design. 428–431. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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