Shen‐Fu Hsiao

1.1k total citations
98 papers, 776 citations indexed

About

Shen‐Fu Hsiao is a scholar working on Computational Theory and Mathematics, Electrical and Electronic Engineering and Signal Processing. According to data from OpenAlex, Shen‐Fu Hsiao has authored 98 papers receiving a total of 776 indexed citations (citations by other indexed papers that have themselves been cited), including 43 papers in Computational Theory and Mathematics, 42 papers in Electrical and Electronic Engineering and 39 papers in Signal Processing. Recurrent topics in Shen‐Fu Hsiao's work include Numerical Methods and Algorithms (41 papers), Digital Filter Design and Implementation (37 papers) and Low-power high-performance VLSI design (25 papers). Shen‐Fu Hsiao is often cited by papers focused on Numerical Methods and Algorithms (41 papers), Digital Filter Design and Implementation (37 papers) and Low-power high-performance VLSI design (25 papers). Shen‐Fu Hsiao collaborates with scholars based in Taiwan, United States and Singapore. Shen‐Fu Hsiao's co-authors include Jean-Marc Delosme, Yu Hen Hu, Kun-Chih Chen, Yi‐Hau Chen, Pramod Kumar Meher, Jen‐Yin Chen, P. S. Wei, Wen-Ling Wang, Ing-Jer Huang and Yun-Nan Chang and has published in prestigious journals such as IEEE Transactions on Signal Processing, IEEE Transactions on Computers and IEEE Transactions on Circuits and Systems for Video Technology.

In The Last Decade

Shen‐Fu Hsiao

83 papers receiving 702 citations

Peers

Countries citing papers authored by Shen‐Fu Hsiao

Since Specialization

Citations

This map shows the geographic impact of Shen‐Fu Hsiao's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shen‐Fu Hsiao with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shen‐Fu Hsiao more than expected).

Fields of papers citing papers by Shen‐Fu Hsiao

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Shen‐Fu Hsiao. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shen‐Fu Hsiao. The network helps show where Shen‐Fu Hsiao may publish in the future.

Co-authorship network of co-authors of Shen‐Fu Hsiao

This figure shows the co-authorship network connecting the top 25 collaborators of Shen‐Fu Hsiao. A scholar is included among the top collaborators of Shen‐Fu Hsiao based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Shen‐Fu Hsiao. Shen‐Fu Hsiao is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Neural Network Acceleration Using Digit-Plane Computation with Early Termination 2024 ·Shen‐Fu Hsiao, (unknown), (unknown), Kun-Chih Chen	1
2	Hardware Accelerator for MobileViT Vision Transformer with Reconfigurable Computation 2024 ·Shen‐Fu Hsiao, (unknown), (unknown), Kun-Chih Chen	1
3	A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition 2022 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Chua‐Chin Wang, (unknown), (unknown), (unknown), (unknown), Shen‐Fu Hsiao, Chia-Hung Yeh	2
4	Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination 2022 ·2022 IEEE International Symposium on Circuits and Systems (ISCAS) ·Shen‐Fu Hsiao, (unknown), (unknown), (unknown)	1
5	Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation 2021 ·Shen‐Fu Hsiao, Jianming Chen, (unknown), (unknown), (unknown)	4
6	Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations 2020 ·IEEE Journal on Emerging and Selected Topics in Circuits and Systems ·Shen‐Fu Hsiao, Kun-Chih Chen, (unknown), (unknown), (unknown)	17
7	Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks 2018 ·Shen‐Fu Hsiao, Yu‐Chang Chen, (unknown)	0
8	Hierarchical Multipartite Function Evaluation 2016 ·IEEE Transactions on Computers ·Shen‐Fu Hsiao, (unknown), Yi‐Hau Chen, (unknown)	17
9	Design of low-leakage multi-port SRAM for register file in graphics processing unit 2014 ·Shen‐Fu Hsiao, (unknown)	12
10	Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units 2013 ·Shen‐Fu Hsiao, (unknown), (unknown), (unknown)	6
11	Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system 2012 ·Shen‐Fu Hsiao, (unknown), (unknown), (unknown)	2
12	A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation 2010 ·(unknown), Shen‐Fu Hsiao, (unknown)	8
13	Low-cost design of reciprocal function units using shared multipliers and adders for polynomial approximation and Newton Raphson interpolation 2010 ·Shen‐Fu Hsiao, (unknown), (unknown)	4
14	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits 2006 ·Shen‐Fu Hsiao, (unknown), (unknown)	2
15	Para-CORDIC: Parallel CORDIC Rotation Algorithm 2004 ·IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ·(unknown), Shen‐Fu Hsiao, (unknown)	71
16	Partition methodology for the final adder in a tree-structure parallel multiplier generator 2003 ·Tso‐Bing Juang, (unknown), (unknown), Shen‐Fu Hsiao	1
17	A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations 2003 ·Shen‐Fu Hsiao	0
18	New unified VLSI architectures for computing DFT and other transforms 2002 ·Shen‐Fu Hsiao, (unknown)	3
19	Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits 2001 ·European Solid-State Circuits Conference ·(unknown), (unknown), Shen‐Fu Hsiao	1
20	Efficient synthesiser for generation of fast parallel multipliers 2000 ·IEE Proceedings - Computers and Digital Techniques ·Shen‐Fu Hsiao, (unknown)	1

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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