Anindya Sundar Dhar

999 total citations
115 papers, 729 citations indexed

About

Anindya Sundar Dhar is a scholar working on Electrical and Electronic Engineering, Signal Processing and Computational Theory and Mathematics. According to data from OpenAlex, Anindya Sundar Dhar has authored 115 papers receiving a total of 729 indexed citations (citations by other indexed papers that have themselves been cited), including 69 papers in Electrical and Electronic Engineering, 52 papers in Signal Processing and 39 papers in Computational Theory and Mathematics. Recurrent topics in Anindya Sundar Dhar's work include Digital Filter Design and Implementation (37 papers), Numerical Methods and Algorithms (29 papers) and Low-power high-performance VLSI design (20 papers). Anindya Sundar Dhar is often cited by papers focused on Digital Filter Design and Implementation (37 papers), Numerical Methods and Algorithms (29 papers) and Low-power high-performance VLSI design (20 papers). Anindya Sundar Dhar collaborates with scholars based in India, United States and Germany. Anindya Sundar Dhar's co-authors include B. Lakshmi, Swapna Banerjee, Kailash Chandra Ray, Koushik Maharatna, Vinay Chakravarthi Gogineni, Ashis Kumar Mal, Indrajit Chakrabarti, Arindam Basu, Mrityunjoy Chakraborty and Amitava Ghosh and has published in prestigious journals such as Electronics Letters, Signal Processing and IEEE Sensors Journal.

In The Last Decade

Anindya Sundar Dhar

104 papers receiving 684 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Anindya Sundar Dhar India 13 370 369 349 111 99 115 729
Martin Kumm Germany 17 249 0.7× 433 1.2× 239 0.7× 191 1.7× 131 1.3× 52 701
Shen‐Fu Hsiao Taiwan 15 368 1.0× 369 1.0× 348 1.0× 150 1.4× 132 1.3× 98 776
Ray Andraka United States 4 241 0.7× 283 0.8× 339 1.0× 121 1.1× 59 0.6× 6 645
Paulo Flores Portugal 15 404 1.1× 372 1.0× 360 1.0× 189 1.7× 101 1.0× 81 731
Shousheng He Sweden 7 563 1.5× 481 1.3× 265 0.8× 87 0.8× 61 0.6× 8 790
M. Torkelson Sweden 11 606 1.6× 593 1.6× 271 0.8× 134 1.2× 120 1.2× 36 933
Julio Villalba Spain 14 338 0.9× 238 0.6× 406 1.2× 131 1.2× 38 0.4× 51 644
Tso‐Bing Juang Taiwan 7 295 0.8× 330 0.9× 406 1.2× 58 0.5× 57 0.6× 30 574
Rajeev Jain United States 16 229 0.6× 405 1.1× 134 0.4× 213 1.9× 145 1.5× 64 794
Wonyong Sung South Korea 11 324 0.9× 208 0.6× 279 0.8× 277 2.5× 45 0.5× 33 703

Countries citing papers authored by Anindya Sundar Dhar

Since Specialization
Citations

This map shows the geographic impact of Anindya Sundar Dhar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anindya Sundar Dhar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anindya Sundar Dhar more than expected).

Fields of papers citing papers by Anindya Sundar Dhar

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Anindya Sundar Dhar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anindya Sundar Dhar. The network helps show where Anindya Sundar Dhar may publish in the future.

Co-authorship network of co-authors of Anindya Sundar Dhar

This figure shows the co-authorship network connecting the top 25 collaborators of Anindya Sundar Dhar. A scholar is included among the top collaborators of Anindya Sundar Dhar based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Anindya Sundar Dhar. Anindya Sundar Dhar is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Dhar, Anindya Sundar, et al.. (2023). Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling. Circuits Systems and Signal Processing. 42(12). 7275–7296. 1 indexed citations
2.
3.
Dhar, Anindya Sundar, et al.. (2022). An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom. Circuits Systems and Signal Processing. 42(3). 1860–1872. 2 indexed citations
4.
Dhar, Anindya Sundar, et al.. (2021). ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design. IEEE Transactions on Emerging Topics in Computing. 10(4). 2072–2078. 4 indexed citations
5.
Dhar, Anindya Sundar, et al.. (2021). A Novel Nested Array for Real-Valued Sources Exploiting Array Motion. IEEE Signal Processing Letters. 28. 1375–1379. 11 indexed citations
6.
Dhar, Anindya Sundar, et al.. (2019). Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy. 63–68.
7.
Gogineni, Vinay Chakravarthi, et al.. (2019). Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27(5). 1223–1227. 9 indexed citations
8.
Dhar, Anindya Sundar, et al.. (2019). Triple transistor based triple modular redundancy with embedded voter circuit. Microelectronics Journal. 87. 101–109. 7 indexed citations
9.
Ghosh, Amitava, et al.. (2017). Fraction phase based low energy frequency calibration: analysis and design. IET Circuits Devices & Systems. 11(3). 241–249. 1 indexed citations
10.
Dhar, Anindya Sundar, et al.. (2017). Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. Journal of Electronic Testing. 33(4). 529–537. 10 indexed citations
11.
Dhar, Anindya Sundar, et al.. (2016). Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. 433–438. 11 indexed citations
12.
Dhar, Anindya Sundar, et al.. (2016). Real-time area efficient and high speed architecture design of Viterbi decoder. 246–250. 3 indexed citations
13.
Dhar, Anindya Sundar, et al.. (2012). A discrete time continuous level VLSI architecture in current mode to implement Discrete Haar Wavelet Transform. Analog Integrated Circuits and Signal Processing. 73(1). 353–362. 2 indexed citations
14.
Dhar, Anindya Sundar, et al.. (2012). Sampled analog VLSI architecture to implement discrete Daubechies wavelet transform. 1. 1–6. 1 indexed citations
15.
Lakshmi, B. & Anindya Sundar Dhar. (2011). VLSI architecture for low latency radix-4 CORDIC. Computers & Electrical Engineering. 37(6). 1032–1042. 20 indexed citations
16.
Ray, Kailash Chandra, et al.. (2010). FPGA implementation of discrete fractional Fourier transform. 1–5. 13 indexed citations
17.
Mal, Ashis Kumar & Anindya Sundar Dhar. (2004). Analog VLSI architecture for discrete cosine transform using dynamic switched capacitors. 666–669. 2 indexed citations
18.
Maharatna, Koushik, Anindya Sundar Dhar, & Swapna Banerjee. (2001). A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Processing. 81(9). 1813–1822. 42 indexed citations
19.
Maharatna, Koushik, et al.. (1997). A 52 MHz 1.5V 16 Bit High Performance Shifter Circuit. 5. 478–480. 1 indexed citations
20.
Dhar, Anindya Sundar, et al.. (1995). Multiplierless array architecture for computing Discrete Cosine Transform. Computers & Electrical Engineering. 21(1). 13–19. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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