Shail Aditya

730 citations
17 papers · 472 indexed · h-index 13

Impact in

Papers in

    • Parallel Computing and Optimization Techniques 11
    • Embedded Systems Design Techniques 11
    • VLSI and Analog Circuit Testing 2
    • Software Testing and Debugging Techniques 6

Shail Aditya

17 papers receiving 426 citations

Peers

Shail Aditya
Comparison fields: 5 of 28
  • Hardware and Architecture 412
  • Computer Networks and Communications 261
  • Software 15
  • Artificial Intelligence 90
  • Computational Theory and Mathematics 37
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Citations per field
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Citations per year

Countries citing papers authored by Shail Aditya

Since Specialization
Citations

This map shows the geographic impact of Shail Aditya's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shail Aditya with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shail Aditya more than expected).

Fields of papers citing papers by Shail Aditya

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Shail Aditya. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shail Aditya. The network helps show where Shail Aditya may publish in the future.

Co-authors

The 13 scholars most cited alongside Shail Aditya, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Shail Aditya Line = papers co-authored together Shail Aditya links everyone, so they are left out of the graph.

All Works

17 of 17 papers shown
#Work
1 200322
2 200279
3 200249
4 2002113
5 200214
6 20019
7
Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors
200011
8 200019
9
Automatic Design of VLIW and EPIC Instruction Formats
200012
10 199950
11 199922
12
Elcor’s Machine Description System: Version 3.0
199817
13 19953
14 19944
15 199421
16 199312
17 199115

About Shail Aditya

Shail Aditya is a scholar working on Hardware and Architecture, Software, Artificial Intelligence, Computer Networks and Communications and Computational Theory and Mathematics, having authored 17 papers that have together received 472 indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (11 papers), Embedded Systems Design Techniques (11 papers), Software Testing and Debugging Techniques (6 papers), Logic, programming, and type systems (5 papers), Interconnection Networks and Systems (3 papers), VLSI and Analog Circuit Testing (2 papers), Algorithms and Data Compression (2 papers) and VLSI and FPGA Design Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (412 citations), Computer Networks and Communications (261 citations), Software (15 citations), Artificial Intelligence (90 citations) and Computational Theory and Mathematics (37 citations). Shail Aditya has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include B. Ramakrishna Rau, Vinod Kathail, Robert Schreiber, D.C. Cronquist, Scott Mahlke, James E. Hicks, Rishiyur S. Nikhil, Christine H. Flood, S.G. Abraham and Gregory L. Snider. Their work appears in journals such as Computer, ACM Transactions on Design Automation of Electronic Systems, Lecture notes in computer science, Design Automation for Embedded Systems and The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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