S. Pullela

801 citations

13 papers · 560 indexed · h-index 10

Co-authors: L.T. Pillage Noel Menezes N. Menezes Lawrence T. Pileggi Florentin Dartu A. Dharchoudhury Rajesh Panda S. V. Gavrilov
Topics: Low-power high-performance VLSI design (13 papers)VLSI and FPGA Design Techniques (11 papers)VLSI and Analog Circuit Testing (9 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Statistical and Nonlinear Physics
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsInternational Conference on Computer Aided DesignThe Journal of VLSI Signal Processing Systems for Signal Image and Video Technology
Partner nations: United States Russia

In The Last Decade

S. Pullela

13 papers receiving 530 citations

Peers

Countries citing papers authored by S. Pullela

Since Specialization

Citations

This map shows the geographic impact of S. Pullela's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Pullela with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Pullela more than expected).

Fields of papers citing papers by S. Pullela

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Pullela. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Pullela. The network helps show where S. Pullela may publish in the future.

Co-authorship network of co-authors of S. Pullela

This figure shows the co-authorship network connecting the top 25 collaborators of S. Pullela. A scholar is included among the top collaborators of S. Pullela based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Pullela. S. Pullela is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

13 of 13 papers shown

#	Work	Indexed citations
1	Skew And Delay Optimization For Reliable Buffered Clock Trees 2005 ·S. Pullela,N. Menezes,(unknown),L.T. Pillage	27
2	Low power IC clock tree design 2002 ·S. Pullela,N. Menezes,L.T. Pillage	12
3	Skew reduction in clock trees using wire width optimization 2002 ·N. Menezes,(unknown),S. Pullela,L.T. Pillage	7
4	Library-less synthesis for static CMOS combinational logic circuits 1997 ·International Conference on Computer Aided Design ·S. V. Gavrilov,(unknown),S. Pullela,(unknown),A. Dharchoudhury,Rajesh Panda,(unknown),David Blaauw	28
5	Transistor-level sizing and timing verification of domino circuits in the Power PC/sup TM/ microprocessor 1997 ·A. Dharchoudhury,David Blaauw,(unknown),S. Pullela,(unknown)	17
6	Clock Distribution Methodology for PowerPC™ Microprocessors 1997 ·The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ·(unknown),(unknown),S. Pullela	2
7	Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets 1997 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·S. Pullela,N. Menezes,Lawrence T. Pileggi	23
8	Post-processing of clock trees via wiresizing and buffering for robust design 1996 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·S. Pullela,N. Menezes,Lawrence T. Pileggi	9
9	Simultaneous gate and interconnect sizing for circuit-level delay optimization 1995 ·Noel Menezes,S. Pullela,Lawrence T. Pileggi	20
10	RC interconnect synthesis—a moment fitting approach 1994 ·International Conference on Computer Aided Design ·Noel Menezes,S. Pullela,Florentin Dartu,L.T. Pillage	42
11	Modeling the "Effective capacitance" for the RC interconnect of CMOS gates 1994 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),S. Pullela,L.T. Pillage	253
12	Reliable non-zero skew clock trees using wire width optimization 1993 ·S. Pullela,Noel Menezes,L.T. Pillage	80
13	Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer 1992 ·(unknown),S. Pullela,L.T. Pillage	40

About S. Pullela

S. Pullela is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Infectious Diseases, having authored 13 papers that have together received 560 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (13 papers), VLSI and FPGA Design Techniques (11 papers) and VLSI and Analog Circuit Testing (9 papers). The work is most often cited by research in Hardware and Architecture (336 citations), Electrical and Electronic Engineering (545 citations) and Statistical and Nonlinear Physics (22 citations). S. Pullela has collaborated with scholars based in United States and Russia. Frequent co-authors include L.T. Pillage, Noel Menezes, N. Menezes, Lawrence T. Pileggi, Florentin Dartu, A. Dharchoudhury, Rajesh Panda, S. V. Gavrilov, David Blaauw and David Blaauw. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, International Conference on Computer Aided Design and The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact