S. Pullela

801 total citations
13 papers, 560 citations indexed

About

S. Pullela is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Infectious Diseases. According to data from OpenAlex, S. Pullela has authored 13 papers receiving a total of 560 indexed citations (citations by other indexed papers that have themselves been cited), including 13 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 0 papers in Infectious Diseases. Recurrent topics in S. Pullela's work include Low-power high-performance VLSI design (13 papers), VLSI and FPGA Design Techniques (11 papers) and VLSI and Analog Circuit Testing (9 papers). S. Pullela is often cited by papers focused on Low-power high-performance VLSI design (13 papers), VLSI and FPGA Design Techniques (11 papers) and VLSI and Analog Circuit Testing (9 papers). S. Pullela collaborates with scholars based in United States and Russia. S. Pullela's co-authors include L.T. Pillage, Noel Menezes, N. Menezes, Lawrence T. Pileggi, Florentin Dartu, A. Dharchoudhury, Rajesh Panda, S. V. Gavrilov, David Blaauw and David Blaauw and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, International Conference on Computer Aided Design and The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology.

In The Last Decade

S. Pullela

13 papers receiving 530 citations

Peers

S. Pullela

EEE

HA

BE

CNC

SNP

N. Menezes United States

Florentin Dartu United States

Noel Menezes United States

Bogdan Tutuianu United States

T. G. McNamara United States

D.H. Allen United States

S. Bobba United States

P. J. Camporese United States

Zhigang Pan United States

Gustavo Wilke Brazil

N. Menezes United States

S. Pullela

422 ×0.8

EEE

266 ×0.8

HA

36 ×0.8

BE

58 ×1.9

CNC

14 ×0.6

SNP

Citations per year, relative to S. Pullela S. Pullela (= 1×) peers N. Menezes

Countries citing papers authored by S. Pullela

Since Specialization

Citations

This map shows the geographic impact of S. Pullela's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Pullela with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Pullela more than expected).

Fields of papers citing papers by S. Pullela

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Pullela. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Pullela. The network helps show where S. Pullela may publish in the future.

Co-authorship network of co-authors of S. Pullela

This figure shows the co-authorship network connecting the top 25 collaborators of S. Pullela. A scholar is included among the top collaborators of S. Pullela based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Pullela. S. Pullela is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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13 of 13 papers shown

1.

Pullela, S., et al.. (2005). Skew And Delay Optimization For Reliable Buffered Clock Trees. 556–562. 27 indexed citations

2.

Pullela, S., N. Menezes, & L.T. Pillage. (2002). Low power IC clock tree design. 263–266. 12 indexed citations

3.

Menezes, N., et al.. (2002). Skew reduction in clock trees using wire width optimization. 9.6.1–9.6.4. 7 indexed citations

4.

Gavrilov, S. V., et al.. (1997). Library-less synthesis for static CMOS combinational logic circuits. International Conference on Computer Aided Design. 658–662. 28 indexed citations

5.

Dharchoudhury, A., et al.. (1997). Transistor-level sizing and timing verification of domino circuits in the Power PC/sup TM/ microprocessor. 143–148. 17 indexed citations

6.

Pullela, S., et al.. (1997). Clock Distribution Methodology for PowerPC™ Microprocessors. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 16(2-3). 181–189. 2 indexed citations

7.

Pullela, S., N. Menezes, & Lawrence T. Pileggi. (1997). Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16(2). 210–215. 23 indexed citations

8.

Pullela, S., N. Menezes, & Lawrence T. Pileggi. (1996). Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15(6). 691–701. 9 indexed citations

9.

Menezes, Noel, S. Pullela, & Lawrence T. Pileggi. (1995). Simultaneous gate and interconnect sizing for circuit-level delay optimization. 690–695. 20 indexed citations

10.

Menezes, Noel, S. Pullela, Florentin Dartu, & L.T. Pillage. (1994). RC interconnect synthesis—a moment fitting approach. International Conference on Computer Aided Design. 418–425. 42 indexed citations

11.

Pullela, S., et al.. (1994). Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13(12). 1526–1535. 253 indexed citations

12.

Pullela, S., Noel Menezes, & L.T. Pillage. (1993). Reliable non-zero skew clock trees using wire width optimization. 165–170. 80 indexed citations

13.

Pullela, S., et al.. (1992). Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer. 15.6.1–15.6.4. 40 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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