Naveen Suda

4.1k total citations · 2 hit papers
15 papers, 1.1k citations indexed

About

Naveen Suda is a scholar working on Electrical and Electronic Engineering, Computer Vision and Pattern Recognition and Biomedical Engineering. According to data from OpenAlex, Naveen Suda has authored 15 papers receiving a total of 1.1k indexed citations (citations by other indexed papers that have themselves been cited), including 11 papers in Electrical and Electronic Engineering, 7 papers in Computer Vision and Pattern Recognition and 5 papers in Biomedical Engineering. Recurrent topics in Naveen Suda's work include Analog and Mixed-Signal Circuit Design (5 papers), Advanced Neural Network Applications (5 papers) and CCD and CMOS Imaging Sensors (3 papers). Naveen Suda is often cited by papers focused on Analog and Mixed-Signal Circuit Design (5 papers), Advanced Neural Network Applications (5 papers) and CCD and CMOS Imaging Sensors (3 papers). Naveen Suda collaborates with scholars based in United States, China and India. Naveen Suda's co-authors include Vikas Chandra, Yu Cao, Jae-sun Seo, Sarma Vrudhula, Yufei Ma, Liangzhen Lai, Abinash Mohanty, Ganesh Dasika, Hardik Sharma and Joon Kyung Kim and has published in prestigious journals such as IEEE Transactions on Power Electronics, IEEE Transactions on Circuits and Systems I Regular Papers and Analog Integrated Circuits and Signal Processing.

In The Last Decade

Naveen Suda

15 papers receiving 1.1k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

2016 393 citations Naveen Suda, Vikas Chandra et al. profile →
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

2018 344 citations Hardik Sharma, Jongse Park et al. profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Naveen Suda United States	10	686	624	411	191	120	15	1.1k
Fengbin Tu China	18	561 0.8×	820 1.3×	398 1.0×	250 1.3×	127 1.1×	64	1.3k
Bert Moons Belgium	12	438 0.6×	780 1.3×	296 0.7×	152 0.8×	117 1.0×	18	1.1k
Jinmook Lee South Korea	15	711 1.0×	830 1.3×	383 0.9×	146 0.8×	101 0.8×	25	1.2k
Sanghoon Kang South Korea	15	606 0.9×	667 1.1×	302 0.7×	112 0.6×	81 0.7×	48	1.1k
Berin Martini United States	10	589 0.9×	617 1.0×	248 0.6×	148 0.8×	58 0.5×	13	948
Liangzhen Lai United States	14	415 0.6×	530 0.8×	316 0.8×	171 0.9×	94 0.8×	31	977
Robert Fasthuber Belgium	6	488 0.7×	582 0.9×	227 0.6×	217 1.1×	141 1.2×	17	851
Yingyan Lin United States	19	522 0.8×	393 0.6×	472 1.1×	141 0.7×	187 1.6×	81	1.1k
Hiroki Nakahara Japan	16	485 0.7×	511 0.8×	321 0.8×	202 1.1×	110 0.9×	98	971
Liqiang He China	6	664 1.0×	802 1.3×	463 1.1×	246 1.3×	158 1.3×	20	1.3k

Countries citing papers authored by Naveen Suda

Since Specialization

Citations

This map shows the geographic impact of Naveen Suda's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Naveen Suda with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Naveen Suda more than expected).

Fields of papers citing papers by Naveen Suda

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Naveen Suda. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Naveen Suda. The network helps show where Naveen Suda may publish in the future.

Co-authorship network of co-authors of Naveen Suda

This figure shows the co-authorship network connecting the top 25 collaborators of Naveen Suda. A scholar is included among the top collaborators of Naveen Suda based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Naveen Suda. Naveen Suda is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

15 of 15 papers shown

1.

Suda, Naveen, et al.. (2019). EdgeAl: A Vision for Deep Learning in the IoT Era. IEEE Design and Test. 38(4). 37–43. 13 indexed citations

2.

Lai, Liangzhen, et al.. (2019). SenseHAR. 15–28. 36 indexed citations

3.

Sharma, Hardik, Jongse Park, Naveen Suda, et al.. (2018). Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network. 764–775. 344 indexed citations breakdown →

4.

Lai, Liangzhen & Naveen Suda. (2018). Enabling deep learning at the IoT edge. 1–6. 33 indexed citations

5.

Ma, Yufei, Naveen Suda, Yu Cao, Sarma Vrudhula, & Jae-sun Seo. (2018). ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integration. 62. 14–23. 68 indexed citations

6.

Li, Meng, Liangzhen Lai, Naveen Suda, Vikas Chandra, & David Z. Pan. (2017). PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.. arXiv (Cornell University). 9 indexed citations

7.

Mohanty, Abinash, Deepak Kadetotad, Naveen Suda, et al.. (2017). A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. 21–22. 1 indexed citations

8.

Suda, Naveen, et al.. (2016). A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Transactions on Circuits and Systems I Regular Papers. 63(2). 181–190. 20 indexed citations

9.

Suda, Naveen, Vikas Chandra, Ganesh Dasika, et al.. (2016). Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. 16–25. 393 indexed citations breakdown →

10.

Suda, Naveen, et al.. (2016). A Low-Noise Output Capacitorless Low-Dropout Regulator With a Switched-RC Bandgap Reference. IEEE Transactions on Power Electronics. 32(4). 2856–2864. 30 indexed citations

11.

Ma, Yufei, Naveen Suda, Yu Cao, Jae-sun Seo, & Sarma Vrudhula. (2016). Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. 1–8. 111 indexed citations

12.

Mohanty, Abinash, Naveen Suda, Minkyu Kim, et al.. (2016). High-performance face detection with CPU-FPGA acceleration. 117–120. 5 indexed citations

13.

Suda, Naveen, et al.. (2015). A 14.8μV<inf>RMS</inf> integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference. 1–4. 4 indexed citations

14.

Suda, Naveen, et al.. (2014). A 0.5-V low power analog front-end for heart-rate detector. Analog Integrated Circuits and Signal Processing. 81(2). 417–430. 14 indexed citations

15.

Suda, Naveen, et al.. (2013). Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Transactions on Circuits and Systems I Regular Papers. 60(6). 1369–1380. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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