Mateusz Majer

511 total citations
20 papers, 297 citations indexed

About

Mateusz Majer is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Mateusz Majer has authored 20 papers receiving a total of 297 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Hardware and Architecture, 10 papers in Computer Networks and Communications and 8 papers in Electrical and Electronic Engineering. Recurrent topics in Mateusz Majer's work include Embedded Systems Design Techniques (14 papers), Interconnection Networks and Systems (9 papers) and VLSI and FPGA Design Techniques (5 papers). Mateusz Majer is often cited by papers focused on Embedded Systems Design Techniques (14 papers), Interconnection Networks and Systems (9 papers) and VLSI and FPGA Design Techniques (5 papers). Mateusz Majer collaborates with scholars based in Germany, Czechia and Japan. Mateusz Majer's co-authors include Jürgen Teich, Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jan C. van der Veen, Jan van der Veen, Dirk Koch, Diana Göhringer, Mirosław A. Czarnecki and Yukihiro Ozaki and has published in prestigious journals such as Applied Spectroscopy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and it - Information Technology.

In The Last Decade

Mateusz Majer

20 papers receiving 270 citations

Peers

Countries citing papers authored by Mateusz Majer

Since Specialization

Citations

This map shows the geographic impact of Mateusz Majer's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mateusz Majer with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mateusz Majer more than expected).

Fields of papers citing papers by Mateusz Majer

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mateusz Majer. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mateusz Majer. The network helps show where Mateusz Majer may publish in the future.

Co-authorship network of co-authors of Mateusz Majer

This figure shows the co-authorship network connecting the top 25 collaborators of Mateusz Majer. A scholar is included among the top collaborators of Mateusz Majer based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Mateusz Majer. Mateusz Majer is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Web-Based Simulator of Superscalar RISC-V Processors 2024 ·Jiří Jaroš, Mateusz Majer, (unknown), J. Va’vra	1
2	Solvent Effect on Assembling and Interactions in Solutions of Phenol: Infrared Spectroscopic and Density Functional Theory Study 2021 ·Applied Spectroscopy ·(unknown), Mateusz Majer, Mirosław A. Czarnecki, Yusuke Morisawa, Yukihiro Ozaki	8
3	Acoustic wave sensor system design consideration 2012 ·(unknown), Mateusz Majer, M. Hušák	1
4	Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device 2008 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Sándor P. Fekete, Jan C. van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich	7
5	Co-design Architecture and Implementation for Point-Based Rendering on FPGAs 2008 ·Mateusz Majer, Stefan Wildermann, (unknown), (unknown), Jürgen Teich	1
6	The Erlangen Slot Machine – A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens) 2007 ·it - Information Technology ·(unknown), Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan C. van der Veen	8
7	Scheduling and CommunicationüAware Mapping of HW/SW Modules for Dynamically and Partially Reconfigurable SoC Architectures 2007 ·Sándor P. Fekete, Jan C. van der Veen, (unknown), (unknown), Mateusz Majer, (unknown)	8
8	The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer 2007 ·The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ·Mateusz Majer, Jürgen Teich, Ali Ahmadinia, (unknown)	55
9	A Flexible Reconfiguration Manager for the Erlangen Slot Machine. 2006 ·Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich	2
10	A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices 2006 ·Ali Ahmadinia, Christophe Bobda, (unknown), Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan C. van der Veen	32
11	An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization 2006 ·Mateusz Majer	5
12	Minimizing Communication Cost for Reconfigurable Slot Modules 2006 ·Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich	3
13	The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms 2006 ·Christophe Bobda, Mateusz Majer, Ali Ahmadinia, (unknown), (unknown), Jürgen Teich	43
14	Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine 2006 ·DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) ·Diana Göhringer, Mateusz Majer, Jürgen Teich	3
15	Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. 2005 ·Christophe Bobda, Ali Ahmadinia, (unknown), Mateusz Majer, (unknown)	4
16	Packet Routing in Dynamically Changing Networks on Chip 2005 ·Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich	35
17	The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform 2005 ·Christophe Bobda, Mateusz Majer, Ali Ahmadinia, (unknown), (unknown), Jürgen Teich, Jan van der Veen	42
18	Flexible overhead processing architectures for G.709 optical transport networks 2004 ·TUbilio (Technical University of Darmstadt) ·(unknown), (unknown), Mateusz Majer, Peter Zipf, Manfred Glesner, (unknown)	1
19	Task scheduling for heterogeneous reconfigurable computers 2004 ·Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich	33
20	Adaptive architectures for an OTN processor 2004 ·(unknown), (unknown), Mateusz Majer, Peter Zipf, Manfred Glesner, (unknown), (unknown), (unknown)	5

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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