Mateo Valero

13.6k total citations
452 papers, 7.7k citations indexed

About

Mateo Valero is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Mateo Valero has authored 452 papers receiving a total of 7.7k indexed citations (citations by other indexed papers that have themselves been cited), including 382 papers in Hardware and Architecture, 351 papers in Computer Networks and Communications and 98 papers in Electrical and Electronic Engineering. Recurrent topics in Mateo Valero's work include Parallel Computing and Optimization Techniques (367 papers), Advanced Data Storage Technologies (161 papers) and Interconnection Networks and Systems (150 papers). Mateo Valero is often cited by papers focused on Parallel Computing and Optimization Techniques (367 papers), Advanced Data Storage Technologies (161 papers) and Interconnection Networks and Systems (150 papers). Mateo Valero collaborates with scholars based in Spain, United States and United Kingdom. Mateo Valero's co-authors include Antonio González, Eduard Ayguadé, Francisco J. Cazorla, Adrián Cristal, Alex Ramírez, Josep Llosa, Jesús Labarta, Roger Espasa, Miquel Moretó and Nigel Topham and has published in prestigious journals such as Proceedings of the IEEE, Communications of the ACM and ACM Computing Surveys.

In The Last Decade

Mateo Valero

431 papers receiving 7.2k citations

Peers

Countries citing papers authored by Mateo Valero

Since Specialization

Citations

This map shows the geographic impact of Mateo Valero's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mateo Valero with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mateo Valero more than expected).

Fields of papers citing papers by Mateo Valero

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mateo Valero. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mateo Valero. The network helps show where Mateo Valero may publish in the future.

Co-authorship network of co-authors of Mateo Valero

This figure shows the co-authorship network connecting the top 25 collaborators of Mateo Valero. A scholar is included among the top collaborators of Mateo Valero based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Mateo Valero. Mateo Valero is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Hardware Runtime for Task-Based Programming Models 2019 ·IEEE Transactions on Parallel and Distributed Systems ·(unknown), (unknown), Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero	14
2	On the maturity of parallel applications for asymmetric multi-core processors 2019 ·Journal of Parallel and Distributed Computing ·(unknown), Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badía, Eduard Ayguadé, Mateo Valero	7
3	Using Arm’s scalable vector extension on stencil codes 2019 ·The Journal of Supercomputing ·Adrià Armejach, (unknown), Juan M. Cebrián, (unknown), (unknown), (unknown), Mateo Valero, Marc Casas, Miquel Moretó	10
4	Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers 2018 ·IEEE Transactions on Parallel and Distributed Systems ·(unknown), Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas	3
5	TagTM - accelerating STMs with hardware tags for fast meta-data access 2012 ·Design, Automation, and Test in Europe ·(unknown), (unknown), Saša Tomić, Ferad Zyulkyarov, Adrián Cristal, Osman Ünsal, Mateo Valero	3
6	Task superscalar: using processors as functional units 2010 ·Yoav Etsion, Alex Ramírez, Rosa M. Badía, Eduard Ayguadé, Jesús Labarta, Mateo Valero	6
7	Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture 2009 ·Repositorio Institucional UN - Biblioteca Digital ·Mauricio A. Álvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink	7
8	Runahead Threads to improve SMT performance 2008 ·QRU Quaderns de Recerca en Urbanisme ·(unknown), Alex Pajuelo, Oliverio J. Santana, Mateo Valero	25
9	A dynamic scheduler for balancing HPC applications 2008 ·IEEE International Conference on High Performance Computing, Data, and Analytics ·(unknown), Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero	36
10	unreadTVar: Extending Haskell Software Transactional Memory for Performance. 2007 ·(unknown), Cristian Perfumo, (unknown), Adrián Cristal, Osman Ünsal, Mateo Valero	16
11	High Performance Embedded Architectures and Compilers: First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings (Lecture Notes in Computer Science) 2005 ·Thomas M. Conte, Nacho Navarro, Wen‐mei Hwu, Mateo Valero, Theo Ungerer	1
12	Fetching instruction streams 2002 ·International Symposium on Microarchitecture ·Alex Ramírez, Oliverio J. Santana, Josep-L. Larriba-Pey, Mateo Valero	32
13	Three-dimensional memory vectorization for high bandwidth media memory systems 2002 ·International Symposium on Microarchitecture ·Jesús Corbal, Roger Espasa, Mateo Valero	7
14	On the efficiency of reductions in /spl mu/-SIMD media extensions 2001 ·International Conference on Parallel Architectures and Compilation Techniques ·Jesús Corbal, Roger Espasa, Mateo Valero	7
15	Modulo scheduling with integrated register spilling for clustered VLIW architectures 2001 ·International Symposium on Microarchitecture ·(unknown), Josep Llosa, Eduard Ayguadé, Mateo Valero	47
16	Exploiting a new level of DLP in multimedia applications 1999 ·International Symposium on Microarchitecture ·Jesús Corbal, Mateo Valero, Roger Espasa	41
17	Widening resources: a cost-effective technique for aggressive ILP architectures 1998 ·International Symposium on Microarchitecture ·David López, Josep Llosa, Mateo Valero, Eduard Ayguadé	10
18	Out-of-order vector architectures 1997 ·International Symposium on Microarchitecture ·Roger Espasa, Mateo Valero, James E. Smith	39
19	Automatic generation of loop scheduling for VLIW 1995 ·International Conference on Parallel Architectures and Compilation Techniques ·Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero	0
20	Hypernode reduction modulo scheduling 1995 ·International Symposium on Microarchitecture ·Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González	37

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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