Josep Llosa

1.3k total citations
49 papers, 792 citations indexed

About

Josep Llosa is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Josep Llosa has authored 49 papers receiving a total of 792 indexed citations (citations by other indexed papers that have themselves been cited), including 45 papers in Hardware and Architecture, 32 papers in Computer Networks and Communications and 12 papers in Electrical and Electronic Engineering. Recurrent topics in Josep Llosa's work include Parallel Computing and Optimization Techniques (43 papers), Embedded Systems Design Techniques (20 papers) and Advanced Data Storage Technologies (13 papers). Josep Llosa is often cited by papers focused on Parallel Computing and Optimization Techniques (43 papers), Embedded Systems Design Techniques (20 papers) and Advanced Data Storage Technologies (13 papers). Josep Llosa collaborates with scholars based in Spain, United States and Sweden. Josep Llosa's co-authors include Mateo Valero, Eduard Ayguadé, Antonio González, Adrián Cristal, Daniel Ortega, Xavier Vera, Nigel Topham, David López, Jaume Abella and Stefan M. Freudenberger and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems and ACM Transactions on Programming Languages and Systems.

In The Last Decade

Josep Llosa

45 papers receiving 720 citations

Peers

Josep Llosa
Santosh G. Abraham United States
David R. Ditzel United States
David B. Papworth United States
Rebecca L. Stamm United States
G. Lakshminarayana United States
Andrew R. Pleszkun United States
Brian Koblenz United States
Richard Simoni United States
Steve Tjiang United States
J.T. Rahmeh United States
Santosh G. Abraham United States
Josep Llosa
Citations per year, relative to Josep Llosa Josep Llosa (= 1×) peers Santosh G. Abraham

Countries citing papers authored by Josep Llosa

Since Specialization
Citations

This map shows the geographic impact of Josep Llosa's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Josep Llosa with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Josep Llosa more than expected).

Fields of papers citing papers by Josep Llosa

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Josep Llosa. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Josep Llosa. The network helps show where Josep Llosa may publish in the future.

Co-authorship network of co-authors of Josep Llosa

This figure shows the co-authorship network connecting the top 25 collaborators of Josep Llosa. A scholar is included among the top collaborators of Josep Llosa based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Josep Llosa. Josep Llosa is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Álvarez, Carlos & Josep Llosa. (2010). Uso de mandos interactivos para la evaluación formativa con realimentación rápida. 3(2). 4. 4 indexed citations
2.
Gupta, Manoj, Fermín Sánchez Carracedo, & Josep Llosa. (2009). Hybrid multithreading for VLIW processors. 37–46.
3.
Llosa, Josep, et al.. (2004). Hierarchical clustered register file organization for VLIW processors. QRU Quaderns de Recerca en Urbanisme. ii. 10–10. 14 indexed citations
4.
Vera, Xavier, et al.. (2004). A fast and accurate framework to analyze and optimize cache memory behavior. ACM Transactions on Programming Languages and Systems. 26(2). 263–300. 28 indexed citations
5.
Vera, Xavier, et al.. (2003). Optimizing program locality through CMEs and GAs. International Conference on Parallel Architectures and Compilation Techniques. 68–78. 13 indexed citations
6.
Cristal, Adrián, José F. Martínez, Josep Llosa, & Mateo Valero. (2003). A case for resource-conscious out-of-order processors. 3–10. 4 indexed citations
7.
Llosa, Josep & Stefan M. Freudenberger. (2002). Reduced code size modulo scheduling in the absence of hardware support. International Symposium on Microarchitecture. 99–110. 8 indexed citations
8.
Llosa, Josep, et al.. (2002). A comparative study of modulo scheduling techniques. 2 indexed citations
9.
Llosa, Josep, et al.. (2002). Partitioned schedules for clustered VLIW architectures. Edinburgh Research Explorer. 386–391. 9 indexed citations
10.
Llosa, Josep, et al.. (2001). Modulo scheduling with integrated register spilling for clustered VLIW architectures. International Symposium on Microarchitecture. 160–169. 47 indexed citations
11.
Vera, Xavier, et al.. (2000). A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). 194–198. 9 indexed citations
12.
Vera, Xavier, et al.. (2000). Optimizing cache miss equations polyhedra. ACM SIGARCH Computer Architecture News. 28(1). 43–52. 4 indexed citations
13.
Llosa, Josep, et al.. (1999). Distributed modulo scheduling. Edinburgh Research Explorer. 130–134. 40 indexed citations
14.
López, David, Josep Llosa, Mateo Valero, & Eduard Ayguadé. (1998). Widening resources: a cost-effective technique for aggressive ILP architectures. International Symposium on Microarchitecture. 237–246. 10 indexed citations
15.
Llosa, Josep, et al.. (1998). Modulo scheduling with reduced register pressure. IEEE Transactions on Computers. 47(6). 625–638. 15 indexed citations
16.
López, David, Mateo Valero, Josep Llosa, & Eduard Ayguadé. (1997). Increasing memory bandwidth with wide buses. 12–19. 8 indexed citations
17.
Llosa, Josep, Mateo Valero, & Eduard Ayguadé. (1996). Heuristics for register-constrained software pipelining. International Symposium on Microarchitecture. 250–261. 23 indexed citations
18.
Ayguadé, Eduard, et al.. (1996). Ictíneo: a Tool for Instruction Level Parallelism Research. 2 indexed citations
19.
Llosa, Josep, Antonio González, Eduard Ayguadé, & Mateo Valero. (1996). Swing Modulo Scheduling: A Lifetime-Sensitive Approach. QRU Quaderns de Recerca en Urbanisme. 80–86. 100 indexed citations
20.
Llosa, Josep, Mateo Valero, Eduard Ayguadé, & Antonio González. (1995). Hypernode reduction modulo scheduling. International Symposium on Microarchitecture. 350–360. 37 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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