Masahiro Iida
About
In The Last Decade
Masahiro Iida
77 papers receiving 374 citations
Peers
Comparison fields: 5 of 43
- Electrical and Electronic Engineering 217
- Hardware and Architecture 193
- Fluid Flow and Transfer Processes 95
- Computer Networks and Communications 79
- Computational Mechanics 63
Countries citing papers authored by Masahiro Iida
This map shows the geographic impact of Masahiro Iida's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Masahiro Iida with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Masahiro Iida more than expected).
Fields of papers citing papers by Masahiro Iida
This network shows the impact of papers produced by Masahiro Iida. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Masahiro Iida. The network helps show where Masahiro Iida may publish in the future.
Co-authorship network of co-authors of Masahiro Iida
This figure shows the co-authorship network connecting the top 25 collaborators of Masahiro Iida. A scholar is included among the top collaborators of Masahiro Iida based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Masahiro Iida. Masahiro Iida is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | Gate Level Netlist Function Classification Method Based on R-GCN | 0 |
| 3 | 4 | |
| 4 | 1 | |
| 5 | FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights | 1 |
| 6 | FPGA routing structure based on H-Tree topology | 1 |
| 7 | 3 | |
| 8 | A study of run-time fault detection mechanism for fault-tolerant FPGAs | 1 |
| 9 | 4 | |
| 10 | A Design Framework for Reconfigurable IPs with VLSI CADs | 2 |
| 11 | 1 | |
| 12 | Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core | 0 |
| 13 | Improvement in data communication between PEs for SIMD type processor MX CORE | 0 |
| 14 | A Low-Power Technique using Resource Sharing Approach for Multi-Context Device | 0 |
| 15 | A low power design method using multi-context dynamic reconfiguration | 2 |
| 16 | A Shape Evaluation of Circuit Area for Reconfigurable Logic Device | 1 |
| 17 | Acquisition of box pushing by direct-vision-based reinforcement learning | 12 |
| 18 | Configurable and Reconfigurable Computing for Digital Signal Processing | 10 |
| 19 | A Proposal of Programmable Logic Architecture for Reconfigurable Computing | 6 |
| 20 | A Feasibility Study for Design Education Using 32bit RISC Microprocessor DLX - FPGA | 0 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.