Kwanseo Park

642 total citations
44 papers, 434 citations indexed

About

Kwanseo Park is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Kwanseo Park has authored 44 papers receiving a total of 434 indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Electrical and Electronic Engineering, 9 papers in Biomedical Engineering and 8 papers in Hardware and Architecture. Recurrent topics in Kwanseo Park's work include Advancements in PLL and VCO Technologies (37 papers), Photonic and Optical Devices (23 papers) and Radio Frequency Integrated Circuit Design (19 papers). Kwanseo Park is often cited by papers focused on Advancements in PLL and VCO Technologies (37 papers), Photonic and Optical Devices (23 papers) and Radio Frequency Integrated Circuit Design (19 papers). Kwanseo Park collaborates with scholars based in South Korea, United States and Netherlands. Kwanseo Park's co-authors include Deog‐Kyoon Jeong, Woorham Bae, Jinhyung Lee, Sung‐Yong Cho, Kwang‐Ho Lee, Han-Gon Ko, Jaeduk Han, Gyu-Seob Jeong, Zhaokai Liu and Ayan Biswas and has published in prestigious journals such as IEEE Transactions on Industrial Electronics, IEEE Access and IEEE Journal of Solid-State Circuits.

In The Last Decade

Kwanseo Park

36 papers receiving 432 citations

Peers

Kwanseo Park

EEE

CNC

Ariel Cohen Israel

J. Berthold Germany

Simone Erba Italy

Jaewook Shin South Korea

Ullas Singh United States

Christos Vezyrtzis United States

Davide Tonietto Canada

Afshin Momtaz United States

Guido Albasini Italy

Abu Khari A’ain Malaysia

Ariel Cohen Israel

Kwanseo Park

256 ×0.6

EEE

65 ×0.7

31 ×0.7

15 ×0.8

CNC

6 ×0.7

Citations per year, relative to Kwanseo Park Kwanseo Park (= 1×) peers Ariel Cohen

Countries citing papers authored by Kwanseo Park

Since Specialization

Citations

This map shows the geographic impact of Kwanseo Park's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kwanseo Park with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kwanseo Park more than expected).

Fields of papers citing papers by Kwanseo Park

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kwanseo Park. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kwanseo Park. The network helps show where Kwanseo Park may publish in the future.

Co-authorship network of co-authors of Kwanseo Park

This figure shows the co-authorship network connecting the top 25 collaborators of Kwanseo Park. A scholar is included among the top collaborators of Kwanseo Park based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kwanseo Park. Kwanseo Park is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Jeong, Deog‐Kyoon, et al.. (2024). A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR. IEEE Transactions on Circuits and Systems I Regular Papers. 71(12). 5861–5872.

Liu, Zhaokai, Kyoungtae Lee, Kwanseo Park, et al.. (2024). A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. 1–5.

Jeong, Deog‐Kyoon, et al.. (2024). A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Transactions on Circuits and Systems I Regular Papers. 71(8). 3550–3560.

Park, Kwanseo, et al.. (2023). A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. IEEE Access. 11. 46513–46521. 2 indexed citations

Lee, Kwang‐Ho, et al.. (2022). Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE Journal of Solid-State Circuits. 57(10). 3014–3024. 9 indexed citations

Lee, Kwang-Hoon, et al.. (2022). A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. IEEE Transactions on Circuits & Systems II Express Briefs. 70(2). 381–385. 9 indexed citations

Jeong, Gyu-Seob, et al.. (2021). A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access. 9. 156789–156798. 1 indexed citations

Ko, Han-Gon, et al.. (2021). A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE Journal of Solid-State Circuits. 56(8). 2525–2538. 8 indexed citations

Park, Kwanseo, et al.. (2020). A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 56(5). 1597–1607. 30 indexed citations

10.

Lee, Jinhyung, et al.. (2020). A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE Journal of Solid-State Circuits. 55(8). 2186–2195. 37 indexed citations

11.

Lee, Kwang‐Ho, et al.. (2020). An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Transactions on Circuits & Systems II Express Briefs. 68(2). 622–626. 8 indexed citations

12.

Cho, Sung‐Yong, et al.. (2019). A 2.5–28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Transactions on Circuits & Systems II Express Briefs. 66(12). 1927–1931. 3 indexed citations

13.

Jeong, Gyu-Seob, et al.. (2019). A Modulo-FIR Equalizer for Wireline Communications. IEEE Transactions on Circuits and Systems I Regular Papers. 66(11). 4278–4286. 3 indexed citations

14.

Park, Kwanseo, et al.. (2019). A 10-Gb/s, 0.03-mm², 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE Journal of Solid-State Circuits. 54(10). 2812–2822. 3 indexed citations

15.

Cho, Sung‐Yong, et al.. (2019). A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Transactions on Circuits & Systems II Express Briefs. 66(12). 1932–1936. 6 indexed citations

16.

Park, Kwanseo, et al.. (2018). A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 53(10). 2982–2993. 34 indexed citations

17.

Jeong, Gyu-Seob, Hyungrok Do, Jinhyung Lee, et al.. (2018). 25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Transactions on Circuits & Systems II Express Briefs. 65(10). 1395–1399. 2 indexed citations

18.

Lee, Jinhyung, Kwanseo Park, Kwang‐Ho Lee, & Deog‐Kyoon Jeong. (2018). A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Transactions on Circuits & Systems II Express Briefs. 65(10). 1295–1299. 13 indexed citations

19.

Park, Kwanseo, et al.. (2017). A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Transactions on Circuits & Systems II Express Briefs. 64(12). 1432–1436. 3 indexed citations

20.

Bae, Woorham, et al.. (2016). A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE Journal of Solid-State Circuits. 51(10). 2357–2367. 44 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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