Kodai Ueyoshi

633 citations

22 papers · 455 indexed · h-index 9

Electrical and Electronic Engineering top 10%
Computer Vision and Pattern Recognition top 5%
Artificial Intelligence top 10%
Hardware and Architecture top 10%
Computer Networks and Communications

Co-authors: Masato Motomura Shinya Takamaeda-Yamazaki Kota Ando Tadahiro Kuroda Tetsuya Asai Masayuki Ikebe Mototsugu Hamada Haruyoshi Yonekawa
Topics: Advanced Neural Network Applications (14 papers)Advanced Memory and Neural Computing (13 papers)Machine Learning and ELM (7 papers)
Cited by: Hardware and Architecture Computer Vision and Pattern Recognition Electrical and Electronic Engineering
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Circuits and Systems I Regular Papers IEEE Transactions on Circuits & Systems II Express Briefs
Partner nations: Japan Switzerland Belgium

In The Last Decade

Kodai Ueyoshi

20 papers receiving 449 citations

Peers

Countries citing papers authored by Kodai Ueyoshi

Since Specialization

Citations

This map shows the geographic impact of Kodai Ueyoshi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kodai Ueyoshi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kodai Ueyoshi more than expected).

Fields of papers citing papers by Kodai Ueyoshi

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kodai Ueyoshi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kodai Ueyoshi. The network helps show where Kodai Ueyoshi may publish in the future.

Co-authorship network of co-authors of Kodai Ueyoshi

This figure shows the co-authorship network connecting the top 25 collaborators of Kodai Ueyoshi. A scholar is included among the top collaborators of Kodai Ueyoshi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kodai Ueyoshi. Kodai Ueyoshi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC 2022 ·2022 IEEE International Solid- State Circuits Conference (ISSCC) ·Kodai Ueyoshi,Ioannis A. Papistas,(unknown),(unknown),Vikram Jain,(unknown),Qilin Zheng,(unknown),Peter Vrancx,(unknown),Debjyoti Bhattacharjee,Stefan Cosemans,Arindam Mallik,Peter Debacker,Diederik Verkest,Marian Verhelst	49
2	DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge 2022 ·IEEE Journal of Solid-State Circuits ·(unknown),(unknown),Vikram Jain,Kodai Ueyoshi,Ioannis A. Papistas,(unknown),Qilin Zheng,Debjyoti Bhattacharjee,Arindam Mallik,Peter Debacker,Diederik Verkest,Marian Verhelst	39
3	A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes 2020 ·K. Shiba,(unknown),Kodai Ueyoshi,Kota Ando,(unknown),Shinya Takamaeda-Yamazaki,Masato Motomura,Mototsugu Hamada,Tadahiro Kuroda	3
4	A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS 2020 ·IEEE Transactions on Circuits and Systems I Regular Papers ·K. Shiba,(unknown),Kodai Ueyoshi,Shinya Takamaeda-Yamazaki,Masato Motomura,Mototsugu Hamada,Tadahiro Kuroda	19
5	Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks 2019 ·IEICE Transactions on Information and Systems ·Kota Ando,Kodai Ueyoshi,(unknown),(unknown),(unknown),Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Masato Motomura	1
6	Quantization error-based regularization for hardware-aware neural network training 2018 ·Nonlinear Theory and Its Applications IEICE ·(unknown),(unknown),Kota Ando,Kodai Ueyoshi,Masayuki Ikebe,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki	0
7	Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware 2018 ·Kota Ando,Kodai Ueyoshi,(unknown),(unknown),(unknown),Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Masato Motomura	6
8	QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS 2018 ·Kodai Ueyoshi,Kota Ando,(unknown),Shinya Takamaeda-Yamazaki,(unknown),(unknown),Mototsugu Hamada,Tadahiro Kuroda,Masato Motomura	71
9	Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators 2018 ·Takumi Kudo,Kodai Ueyoshi,Kota Ando,(unknown),(unknown),(unknown),Masayuki Ikebe,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki	0
10	In-memory area-efficient signal streaming processor design for binary neural networks 2017 ·Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Kota Ando,Kodai Ueyoshi,(unknown),(unknown),Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Tetsuya Asai,Masato Motomura	6
11	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W 2017 ·IEEE Journal of Solid-State Circuits ·Kota Ando,Kodai Ueyoshi,(unknown),Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura	115
12	Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA 2017 ·Kodai Ueyoshi,Takao Marukame,Tetsuya Asai,Masato Motomura,Alexandre Schmid	1
13	Logarithmic Compression for Memory Footprint Reduction in Neural Network Training 2017 ·(unknown),(unknown),Kota Ando,(unknown),Kodai Ueyoshi,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Masato Motomura	1
14	BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS 2017 ·Kota Ando,Kodai Ueyoshi,(unknown),Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Tadahiro Kuroda,Masato Motomura	57
15	Exploring optimized accelerator design for binarized convolutional neural networks 2017 ·Kodai Ueyoshi,Kota Ando,(unknown),Masayuki Ikebe,Tetsuya Asai,Masato Motomura	6
16	FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines 2016 ·Circuits and Systems ·Kodai Ueyoshi,Takao Marukame,Tetsuya Asai,Masato Motomura,Alexandre Schmid	11
17	Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation 2016 ·IEEE Transactions on Circuits & Systems II Express Briefs ·Takao Marukame,Kodai Ueyoshi,Tetsuya Asai,Masato Motomura,Alexandre Schmid,(unknown),Y. Higashi,Yuichiro Mitani	13
18	FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting 2016 ·(unknown),Kota Ando,Kodai Ueyoshi,Masayuki Ikebe,Tetsuya Asai,Masato Motomura	4
19	Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing 2016 ·Nonlinear Theory and Its Applications IEICE ·Kodai Ueyoshi,Takao Marukame,Tetsuya Asai,Masato Motomura,Alexandre Schmid	7
20	Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network 2016 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Kodai Ueyoshi,Takao Marukame,Tetsuya Asai,Masato Motomura,Alexandre Schmid	5

About Kodai Ueyoshi

Kodai Ueyoshi is a scholar working on Computer Vision and Pattern Recognition, Artificial Intelligence and Electrical and Electronic Engineering, having authored 22 papers that have together received 455 indexed citations. Recurring topics across this work include Advanced Neural Network Applications (14 papers), Advanced Memory and Neural Computing (13 papers) and Machine Learning and ELM (7 papers). The work is most often cited by research in Hardware and Architecture (63 citations), Computer Vision and Pattern Recognition (185 citations) and Electrical and Electronic Engineering (373 citations). Kodai Ueyoshi has collaborated with scholars based in Japan, Switzerland and Belgium. Frequent co-authors include Masato Motomura, Shinya Takamaeda-Yamazaki, Kota Ando, Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, Mototsugu Hamada, Haruyoshi Yonekawa, Shimpei Sato and Hiroki Nakahara. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Circuits & Systems II Express Briefs.

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