K. Aingaran
- Hardware and Architecture top 1%
- Parallel Computing and Optimization Techniques 2
- VLSI and Analog Circuit Testing 2
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- Distributed systems and fault tolerance 1
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- Low-power high-performance VLSI design 5
- VLSI and FPGA Design Techniques 2
- Advancements in Semiconductor Devices and Circuit Design 1
- Electromagnetic Compatibility and Noise Suppression 1
- Information Systems top 10%
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- Analog and Mixed-Signal Circuit Design 2
- Cited by
- Hardware and ArchitectureComputer Networks and CommunicationsElectrical and Electronic Engineering
- Journals
- IEEE Micro (2 papers)IEEE Journal of Solid-State Circuits (1 paper)International Conference on Computer Aided Design (1 paper)
- Partner nations
- United StatesUnited Kingdom
In The Last Decade
K. Aingaran
8 papers receiving 870 citations
Hit Papers
Peers
Comparison fields: 5 of 38
- Hardware and Architecture 684
- Computer Networks and Communications 608
- Electrical and Electronic Engineering 422
- Information Systems 86
- Computer Graphics and Computer-Aided Design 12
Countries citing papers authored by K. Aingaran
This map shows the geographic impact of K. Aingaran's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Aingaran with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Aingaran more than expected).
Fields of papers citing papers by K. Aingaran
This network shows the impact of papers produced by K. Aingaran. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Aingaran. The network helps show where K. Aingaran may publish in the future.
Co-authorship network
The 15 scholars most cited alongside K. Aingaran, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2016 | 7 | |
| 2 | 2015 | 29 | |
| 3 | Niagara: A 32-Way Multithreaded Sparc Processorbreakdown → | 2005 | 713 |
| 4 | 2002 | 16 | |
| 5 | 2002 | 37 | |
| 6 | 2002 | 1 | |
| 7 | 2001 | 43 | |
| 8 | 1999 | 107 |
About K. Aingaran
K. Aingaran is a scholar working on Hardware and Architecture, Computer Networks and Communications, Electrical and Electronic Engineering, Automotive Engineering and Biomedical Engineering, having authored 8 papers that have together received 953 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (5 papers), VLSI and FPGA Design Techniques (2 papers), Analog and Mixed-Signal Circuit Design (2 papers), Parallel Computing and Optimization Techniques (2 papers), VLSI and Analog Circuit Testing (2 papers), Advancements in Semiconductor Devices and Circuit Design (1 paper), Distributed systems and fault tolerance (1 paper) and Electromagnetic Compatibility and Noise Suppression (1 paper). The work is most often cited by research in Hardware and Architecture (684 citations), Computer Networks and Communications (608 citations), Electrical and Electronic Engineering (422 citations), Information Systems (86 citations) and Computer Graphics and Computer-Aided Design (12 citations). K. Aingaran has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include Poonacha Kongetira, Kunle Olukotun, S. Bobba, F. Klass, Cong Nam Truong, Gin Yee, Anup Das, R. Heald, Dean Liu and Serena Leung. Their work appears in journals such as IEEE Micro, IEEE Journal of Solid-State Circuits and International Conference on Computer Aided Design.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.