Jose Renau
- Hardware and Architecture top 0.5%
- Computer Networks and Communications top 1%
- Electrical and Electronic Engineering top 5%
- Information Systems top 5%
- Artificial Intelligence
- Co-authors
- Josep TorrellasMichael HuangEhsan K. ArdestaniFrancisco J. Mesa-MartínezSeung-Moon YooLuís CezeJames TuckKarin Strauß
- Topics
- Parallel Computing and Optimization Techniques (63 papers)Low-power high-performance VLSI design (36 papers)Embedded Systems Design Techniques (23 papers)
- Cited by
- Hardware and ArchitectureComputer Networks and CommunicationsElectrical and Electronic Engineering
- Journals
- SHILAP Revista de lepidopterologíaIEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsACM SIGPLAN Notices
- Partner nations
- United StatesSpainFrance
In The Last Decade
Jose Renau
77 papers receiving 1.5k citations
Peers
Comparison fields: 5 of 45
- Hardware and Architecture 1.3k
- Computer Networks and Communications 881
- Electrical and Electronic Engineering 700
- Information Systems 193
- Artificial Intelligence 79
Countries citing papers authored by Jose Renau
This map shows the geographic impact of Jose Renau's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jose Renau with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jose Renau more than expected).
Fields of papers citing papers by Jose Renau
This network shows the impact of papers produced by Jose Renau. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jose Renau. The network helps show where Jose Renau may publish in the future.
Co-authorship network of co-authors of Jose Renau
This figure shows the co-authorship network connecting the top 25 collaborators of Jose Renau. A scholar is included among the top collaborators of Jose Renau based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jose Renau. Jose Renau is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 3 | |
| 2 | Securing Processors from Time Side Channels | 1 |
| 3 | 12 | |
| 4 | 2 | |
| 5 | 55 | |
| 6 | 5 | |
| 7 | 94 | |
| 8 | 10 | |
| 9 | 17 | |
| 10 | 38 | |
| 11 | 62 | |
| 12 | 25 | |
| 13 | 14 | |
| 14 | 5 | |
| 15 | 84 | |
| 16 | 6 | |
| 17 | 28 | |
| 18 | The design of DEETM: A framework for dynamic energy efficiency and temperature management | 12 |
| 19 | Energy/performance design of memory hierarchies for processor-in-memory chips | 2 |
| 20 | Memory Hierarchies In Intelligent Memories: Energy/Performance Design | 2 |
About Jose Renau
Jose Renau is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 78 papers that have together received 1.5k indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (63 papers), Low-power high-performance VLSI design (36 papers) and Embedded Systems Design Techniques (23 papers). The work is most often cited by research in Hardware and Architecture (1.3k citations), Computer Networks and Communications (881 citations) and Electrical and Electronic Engineering (700 citations). Jose Renau has collaborated with scholars based in United States, Spain and France. Frequent co-authors include Josep Torrellas, Michael Huang, Ehsan K. Ardestani, Francisco J. Mesa-Martínez, Seung-Moon Yoo, Luís Ceze, James Tuck, Karin Strauß, Wei Liu and Wonsun Ahn. Their work appears in journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and ACM SIGPLAN Notices.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.