Joo‐Hyung Chae

424 total citations
45 papers, 220 citations indexed

About

Joo‐Hyung Chae is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Joo‐Hyung Chae has authored 45 papers receiving a total of 220 indexed citations (citations by other indexed papers that have themselves been cited), including 43 papers in Electrical and Electronic Engineering, 11 papers in Biomedical Engineering and 9 papers in Hardware and Architecture. Recurrent topics in Joo‐Hyung Chae's work include Advancements in PLL and VCO Technologies (31 papers), Radio Frequency Integrated Circuit Design (17 papers) and Semiconductor materials and devices (12 papers). Joo‐Hyung Chae is often cited by papers focused on Advancements in PLL and VCO Technologies (31 papers), Radio Frequency Integrated Circuit Design (17 papers) and Semiconductor materials and devices (12 papers). Joo‐Hyung Chae collaborates with scholars based in South Korea, United States and Puerto Rico. Joo‐Hyung Chae's co-authors include Suhwan Kim, Chang‐Ho Hyun, Jihwan Park, Jihwan Park, Deog‐Kyoon Jeong, Sungjun Kim, Jae Whan Lee, M. Kim, Han-Gon Ko and Jisoo Park and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Access and IEEE Journal of Solid-State Circuits.

In The Last Decade

Joo‐Hyung Chae

38 papers receiving 219 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Joo‐Hyung Chae South Korea 9 204 49 47 16 6 45 220
Kwanseo Park South Korea 13 428 2.1× 89 1.8× 45 1.0× 20 1.3× 6 1.0× 44 434
Stéphane Donnay Belgium 8 311 1.5× 68 1.4× 49 1.0× 17 1.1× 2 0.3× 18 322
M. Sorna United States 10 375 1.8× 72 1.5× 54 1.1× 19 1.2× 18 3.0× 20 385
Fumio Yuki Japan 11 367 1.8× 56 1.1× 38 0.8× 32 2.0× 14 2.3× 28 374
Tomoaki Yabe Japan 11 320 1.6× 44 0.9× 79 1.7× 18 1.1× 5 0.8× 23 330
Roberto Nonis Austria 11 438 2.1× 135 2.8× 21 0.4× 13 0.8× 8 1.3× 35 451
Youngdon Choi South Korea 6 158 0.8× 64 1.3× 27 0.6× 15 0.9× 9 1.5× 21 164
Simone Erba Italy 8 303 1.5× 63 1.3× 43 0.9× 19 1.2× 3 0.5× 18 310
Osamu Hirabayashi Japan 10 333 1.6× 43 0.9× 81 1.7× 19 1.2× 3 0.5× 25 340
Y. Takeyama Japan 12 389 1.9× 45 0.9× 86 1.8× 22 1.4× 6 1.0× 27 399

Countries citing papers authored by Joo‐Hyung Chae

Since Specialization
Citations

This map shows the geographic impact of Joo‐Hyung Chae's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Joo‐Hyung Chae with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Joo‐Hyung Chae more than expected).

Fields of papers citing papers by Joo‐Hyung Chae

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Joo‐Hyung Chae. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Joo‐Hyung Chae. The network helps show where Joo‐Hyung Chae may publish in the future.

Co-authorship network of co-authors of Joo‐Hyung Chae

This figure shows the co-authorship network connecting the top 25 collaborators of Joo‐Hyung Chae. A scholar is included among the top collaborators of Joo‐Hyung Chae based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Joo‐Hyung Chae. Joo‐Hyung Chae is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Lee, Juncheol, et al.. (2025). A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces. IEEE Transactions on Circuits and Systems I Regular Papers. 72(6). 2653–2663.
2.
Chae, Joo‐Hyung, et al.. (2024). Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces. IEEE Transactions on Instrumentation and Measurement. 73. 1–8.
3.
Kim, Donghyuk, Jaeyoung Kim, Suk Jin Lee, et al.. (2024). DPIM: A 19.36 TOPS/W 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core. 141–144. 1 indexed citations
4.
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Chae, Joo‐Hyung, et al.. (2024). A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces. IEEE Transactions on Circuits and Systems I Regular Papers. 71(12). 6306–6315. 2 indexed citations
6.
7.
Chae, Joo‐Hyung. (2024). High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects. SHILAP Revista de lepidopterología. 4. 252–264. 2 indexed citations
8.
Lee, Jong‐Chan & Joo‐Hyung Chae. (2024). Debugging Circuit for Detecting Timing Errors in Serializer for High-Speed Wireline Interfaces. IEEE Access. 12. 164352–164358.
9.
Lee, Wan‐Gyu & Joo‐Hyung Chae. (2023). Improvement of Data Retention Time in Gain-Cell Embedded DRAM Using MOMCAP. 1–5.
10.
Chae, Joo‐Hyung. (2023). Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement. IEEE Transactions on Instrumentation and Measurement. 72. 1–10. 2 indexed citations
11.
Kim, Suhwan, et al.. (2023). Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. IEEE Transactions on Circuits and Systems I Regular Papers. 70(12). 4793–4803. 6 indexed citations
12.
Kim, Suhwan, et al.. (2021). A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. IEEE Journal of Solid-State Circuits. 56(8). 2563–2573. 7 indexed citations
13.
14.
Chae, Joo‐Hyung, et al.. (2021). A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Transactions on Circuits and Systems I Regular Papers. 69(3). 1125–1134. 5 indexed citations
15.
Hyun, Chang‐Ho, et al.. (2020). A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. IEEE Journal of Solid-State Circuits. 56(4). 1278–1287. 35 indexed citations
16.
Ko, Han-Gon, et al.. (2019). A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Transactions on Circuits & Systems II Express Briefs. 67(10). 1735–1739. 2 indexed citations
17.
Chae, Joo‐Hyung, et al.. (2018). A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Transactions on Circuits & Systems II Express Briefs. 65(12). 1894–1898. 9 indexed citations
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20.
Chae, Joo‐Hyung, et al.. (2017). 266–2133 MHz phase shifter using all‐digital delay‐locked loop and triangular‐modulated phase interpolator for LPDDR4X interface. Electronics Letters. 53(12). 766–768. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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