Uri Weiser

5.3k citations

51 papers · 3.7k indexed · 3 hit papers · h-index 21

Impact in

Hardware and Architecture top 0.5%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
Cellular and Molecular Neuroscience top 1%
- Neuroscience and Neural Engineering

Papers in ⓘ

Hardware and Architecture 38
- Parallel Computing and Optimization Techniques 35
- Embedded Systems Design Techniques 8
Computer Networks and Communications 29
- Interconnection Networks and Systems 17
- Advanced Data Storage Technologies 15

Co-authors: Avinoam Kolodny (21 shared papers)Shahar Kvatinsky (10 shared papers)Eby G. Friedman (9 shared papers)Nimrod Wald (3 shared papers)Guy Satat (3 shared papers)Д. Р. Белоусов (1 shared paper)Ran Ginosar (8 shared papers)Avi Mendelson (7 shared papers)
Journals: IEEE Computer Architecture Letters (11 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2 papers)IEEE Circuits and Systems Magazine (2 papers)IEEE Micro (2 papers)Computer (2 papers)
Partner nations: Israel United States United Kingdom

In The Last Decade

Uri Weiser

50 papers receiving 3.5k citations

Hit Papers

align trajectories log scale

MAGIC—Memristor-Aided Logic 2014 · 604 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2014 IEEE Transactions on Circuits & Systems II Express Briefs
2013 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2012 IEEE Transactions on Circuits and Systems I Regular Papers

Peers

Countries citing papers authored by Uri Weiser

Since Specialization

Citations

This map shows the geographic impact of Uri Weiser's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Uri Weiser with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Uri Weiser more than expected).

Fields of papers citing papers by Uri Weiser

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Uri Weiser. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Uri Weiser. The network helps show where Uri Weiser may publish in the future.

Co-authors

The 25 scholars most cited alongside Uri Weiser, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Uri Weiser Line = papers co-authored together Uri Weiser links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 51 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	TEAM: ThrEshold Adaptive Memristor Model IEEE Transactions on Circuits and Systems I Regular Papers ·Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri Weiser Hit paper breakdown →	2012	612
2	MAGIC—Memristor-Aided Logic IEEE Transactions on Circuits & Systems II Express Briefs ·Shahar Kvatinsky, Д. Р. Белоусов, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri Weiser Hit paper breakdown →	2014	604
3	Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri Weiser Hit paper breakdown →	2013	479
4	MMX technology extension to the Intel architecture IEEE Micro ·A. Peleg, Uri Weiser	1996	351
5	Interconnect-power dissipation in a microprocessor Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir	2004	309
6	MRL — Memristor Ratioed Logic Shahar Kvatinsky, Nimrod Wald, Guy Satat, Avinoam Kolodny, Uri Weiser, Eby G. Friedman	2012	186
7	Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors IEEE Computer Architecture Letters ·Tomer Y. Morad, Uri Weiser, Avinoam Kolodny, Mateo Valero, Eduard Ayguadé	2006	116
8	Intel MMX for multimedia PCs Communications of the ACM ·A. Peleg, Sam Wilkie, Uri Weiser	1997	115
9	Memristor-based IMPLY logic design procedure Shahar Kvatinsky, Avinoam Kolodny, Uri Weiser, Eby G. Friedman	2011	112
10	Many-Core vs. Many-Thread Machines: Stay Away From the Valley IEEE Computer Architecture Letters ·Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri Weiser	2009	68
11	Correlated load-address predictors Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser	1999	67
12	Semantic locality and context-based prefetching using reinforcement learning Leeor Peled, Shie Mannor, Uri Weiser, Yoav Etsion	2015	62
13	The Desired Memristor for Circuit Designers IEEE Circuits and Systems Magazine ·Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri Weiser	2013	60
14	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment IEEE Micro ·Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri Weiser	2017	59
15	Models of memristors for SPICE simulations Shahar Kvatinsky, Keren Talisveyberg, Dmitry Fliter, Avinoam Kolodny, Uri Weiser, Eby G. Friedman	2012	54
16	Spatial Correlation and Value Prediction in Convolutional Neural Networks IEEE Computer Architecture Letters ·Gil Shomron, Uri Weiser	2018	35
17	Multiple clock and voltage domains for chip multi processors Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri Weiser	2009	33
18	Correlated load-address predictors Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser	2003	30
19	Utilizing shared data in chip multiprocessors with the Nahalal architecture Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri Weiser	2008	30
20	MultiAmdahl: How Should I Divide My Heterogenous Chip? IEEE Computer Architecture Letters ·Tsahee Zidenberg, Isaac Keslassy, Uri Weiser	2012	29

About Uri Weiser

Uri Weiser is a scholar working on Hardware and Architecture, Computer Networks and Communications, Electrical and Electronic Engineering, Cellular and Molecular Neuroscience and Information Systems, having authored 51 papers that have together received 3.7k indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (35 papers), Interconnection Networks and Systems (17 papers), Advanced Data Storage Technologies (15 papers), Advanced Memory and Neural Computing (10 papers), Neuroscience and Neural Engineering (8 papers), Low-power high-performance VLSI design (8 papers), Embedded Systems Design Techniques (8 papers) and Ferroelectric and Negative Capacitance Devices (8 papers). The work is most often cited by research in Hardware and Architecture (1.2k citations), Cellular and Molecular Neuroscience (1.2k citations), Electrical and Electronic Engineering (2.7k citations), Computer Networks and Communications (951 citations) and Signal Processing (169 citations). Uri Weiser has collaborated with scholars based in Israel, United States and United Kingdom. Frequent co-authors include Avinoam Kolodny, Shahar Kvatinsky, Eby G. Friedman, Nimrod Wald, Guy Satat, Д. Р. Белоусов, Ran Ginosar, Avi Mendelson, Yoav Etsion and Zvika Guz. Their work appears in journals such as IEEE Computer Architecture Letters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Circuits and Systems Magazine, IEEE Micro and Computer.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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